User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 162
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
PL Power-Down
The PL power-down sequence includes stopping the use of all signals between the PS and PL,
disabling the voltage level shifters, and powering off the PL. An example sequence is shown in
section 2.4 PS–PL Voltage Level Shifter Enables.
6.2.3 Clocks and PLLs
The PS_CLK reference clock is routed to multiple sections of the device, including the three PS clock
PLLs. The frequency of the PS_CLK affects the boot time of the device. The PLLs multiply the PS_CLK
to generate high frequency clocks for various system clock modules. When needed, the PLLs can be
bypassed to deliver the PS_CLK frequency directly to the system clock modules.
If the PLLs are enabled, then the PS_CLK must be stable before the PLLs are enabled and must remain
stable. The clock frequency must be within its operating range as specified in the data sheet.
If the PLLs are bypassed, the PS_CLK can be toggled as slow as desired and up to its rated input
frequency. This can be used to single-step the bring-up processes, control the clock with software, or
operate the system at a low clock frequency. Operating the system at a low clock frequency might
preclude the use of some modules within the device (e.g., the USB ULPI clock must be at a lower
frequency than the CPU_1x clock).
The device clocks, PS PLLs, and system clock modules are detailed in Chapter 25, Clocks.
6.2.4 Reset Operations
There are two types of system resets: POR and non-POR. The details of the system resets are
described in Chapter 26, Reset System. All of these resets cause the BootROM to execute.
POR Reset
The POR resets reset the whole system, including all of the registers. All states except the eFuse and
BBRAM are lost.
• PS_POR_B pin, described in more detail, below.
Non-POR Resets
Non-POR reset events are recorded in the slcr.REBOOT_STATUS register. A non-POR reset also causes
the BootROM to execute, but the BootROM retains knowledge about the security level of the
previous boot in the devcfg.CTRL [SEC_EN] bit. Not all of the registers are reset by a non-POR reset,
refer to Table 26-2, page 707.
The non-POR reset sources include:
• PS_SRST_B pin, described in more detail, below.
• Internal system resets