User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 165
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
User Defined Persistent Bit Field
The 16-bit user defined persistent bit field is located in the devcfg.MULTIBOOT_ADDR register, bits
31:16. The [USERDEF_PERSISTENT] bit field can be used to pass status and command information
between one non-POR FSBL/User code boot and another.
6.2.5 Boot Mode Pin Settings
There are 7 boot mode strapping pins that are hardware programmed on the board using MIO pins
[8:2]. They are sampled by the hardware soon after PS_POR_B deasserts and their values are written
to software readable registers for use by the BootROM and user software. The board hardware must
connect each strapping pin, MIO [8:2], to a 20 kΩ pull-up or pull-down resistor. The encoding of the
mode pins are shown in Table 6-4. A pull-up resistor specifies a logic 1 and a pull-down resistor
specifies a logic 0.
Five pins, BOOT_MODE[4:0], are used to select the boot mode, JTAG chain config, and if the PLLs are
bypassed. The sampled values of these pins are written into the slcr.BOOT_MODE [BOOT_MODE] and
[PLL_BYPASS] bit fields.
• Boot modes are explained in section 6.3 BootROM.
• Boot strap pins are listed in Table 6-4.
• JTAG chains are described in section 6.4.5 PL Control via User-JTAG.
• PLLs are described in section 6.2.3 Clocks and PLLs.
Two pins, VMODE[1:0], are used to select the voltage signaling levels for the two MIO voltage banks.
The sampled values of these pins are written into the slcr.GPIOB_DRVR_BIAS_CTRL [RB_VCFG] and
[LB_VCFG] bit fields. The VMODE settings are used by the BootROM to initially set the
MIO_PIN_{53:00} registers to the selected I/O signaling standard. VMODE[0] controls MIO pins 15:0
and VMODE[1] controls MIO pins 53:16. A pull-up causes the BootROM to select LVCMOS18. A
pull-down selects LVCMOS33 which is deemed compatible with LVCMOS25. The MIO pin I/O
programming descriptions are described in the slcr.MIO_PIN_00 register definition in Appendix B,
Register Details.
The FSBL/User code can change the initial boot mode settings for the JTAG chain, the PLLs and the
I/O voltage standard for the MIO pins on individual MIO pin basis.
Resets PL Yes Yes
Notes:
1. The Boot_Mode [4] pin strap determines if the PLLs are enabled or bypassed.
2. There are a number of register and individual register bit fields that are not affected by a non-POR
reset. Refer to Table 26-2, page 707 for a list
.
Table 6-3: System Reset Effects (Cont’d)
Reset Type POR Non-POR