User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 168
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
Secure/Non-Secure
For security reasons, CPU 0 is always the first device out of reset among all master modules within
the PS. CPU 1 is held in an WFE state. While the BootROM is running, JTAG is always disabled,
regardless of the reset type, to ensure security. After the BootROM runs, JTAG is enabled if the boot
mode is non-secure.
The BootROM code is also responsible for loading the FSBL/User code. When the BootROM releases
control to stage 1, user software assumes full control of the entire system. The only way to execute
the BootROM again is by generating one of the system resets. The FSBL/User code size, encrypted
and unencrypted, is limited to 192 KB. This limit does not apply with the non-secure
execute-in-place option.
The PS boot source is selected using the BOOT_MODE strapping pins (indicated by a weak pull-up or
pull-down resistor), which are sampled once during power-on reset (POR). The sampled values are
stored in the slcr.BOOT_MODE register.
The BootROM supports encrypted/authenticated, and unencrypted images referred to as secure boot
and non-secure boot, respectively.
The BootROM supports execution of the stage 1 image directly from NOR or Quad-SPI when using
the execute-in-place option, but only for non secure boot images. Execute-in-place is possible only
for NOR and Quad-SPI boot modes.
In secure boot, the CPU, running the BootROM code, decrypts and authenticates the user PS image
on the boot device, stores it in the OCM, and then branches to it.
In non-secure boot, the CPU, running the BootROM code, disables all secure boot features including
the AES unit within the PL before branching to the user image in the OCM memory or the flash
device (if execute-in-place is used).
Any subsequent boot stages for either the PS or the PL are your responsibility and are under your
control. The BootROM code is not accessible to you. Following a stage 1 secure boot, you can
proceed with either secure or non-secure subsequent boot stages. Following a non-secure first stage
boot, only non-secure subsequent boot stages are possible.
Boot Sources
There are five possible boot sources: NAND, NOR, SD card, Quad-SPI, and JTAG. The first four boot
sources are used in master boot methods in which the CPU loads the external boot image from
nonvolatile memory into the PS.
JTAG is the slave boot mode, and is only supported with a non-secure boot. An external host
computer acts as the master to load the boot image into the OCM through a JTAG connection. The
PS CPU remains in idle mode as the boot image is loaded.
The configuration flow for the BootROM is shown in Figure 6-5.