User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 171
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
Interrupt Table for Execution-in-Place — 0x000 to 0x01C
Eight 32-bit words are reserved for interrupt mapping. This is useful for execute-in-place for NOR
and Quad-SPI devices. It allows the CPU vector table to be managed in two ways. The first is to use
the MMU to remap the flash linear address space to 0x0. The second method to manage the vector
table location is to use the coprocessor VBAR register. For more information on setting this register,
refer to the ARM v7-AR Architecture Reference Manual (listed in Appendix A, Additional Resources).
Width Detection — 0x020
Width Detection is required for the Quad-SPI boot mode. Ensure that the BootROM Header includes
the value of
0xAA995566 so the BootROM can determine the maximum hardware I/O data
connection width of the flash device(s). This value helps the BootROM to determine the data width of
a single Quad-SPI device (x1, x2, or x4) and to detect a second device in 8-bit parallel I/O
configuration. If this value is not present for the Quad-SPI boot mode then the BootROM lockdowns
the system and generates an error code. The error code number depends on other conditions. The
error codes are listed in Table 6-20, page 198. Details of the detection operation are explained in
section 6.3.4 Quad-SPI Boot.
Image Identification — 0x024
This word has a mandatory value of 0x584C4E58,'XLNX'. This value allows the BootROM (along with
the header checksum field) to determine that a valid BootROM Header is present. If the value is not
0x04C - 0x09F 19 - 39 FSBL/User Defined(84-Byte)
(3)
~~~
0x0A0 - 0x89F 40 - 551
Register Initialization
(2048-Byte)
(4)
yes yes yes
0x8A0 - 0x8BF 552 - 559 FSBL/User Defined (32-Byte)
(3)
~~~
0x8C0 560 and up FSBL Image or User Code 192 KB 192 KB see
(5)
Notes:
1. In secure mode, the Total Image Length parameter is greater than Length of Image parameter because of
encryption.
2. In non-secure OCM mode, the Total Image Length parameter must be set equal to the Length of Image parameter.
3. The usages of the FSBL/User Defined areas are explained in UG821, Zynq-7000 All Programmable SoC Software
Developers Guide.
4. The addresses that can be accessed by Register Initialization is restricted, see Table 6-7. The secure boot mode has
more address restrictions than a non-secure boot.
5. The size of the FSBL image (or User code) for Execute-in-place depends on the allowed capacity of the boot device
less the 0x8C0 (the size of the BootROM Header). The maximum Quad-SPI size is described in section
6.3.4 Quad-SPI Boot. For NOR, refer to section 6.3.6 NOR Boot.
6. To select the execute-in-place feature, set the Length of Image and Total Image Length parameters to 0 and load
the PS interconnect address into the Source Offset.
Table 6-5: BootROM Header Parameters (Cont’d)
Header Address
32-bit
Word
Parameter
Boot Device
Secure
Usage
Non-Secure
Usages
OCM OCM
Execute In
Place
(6)