User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 172
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
matched, the BootROM performs a BootROM Header search if the boot mode is either Quad-SPI,
NAND, or NOR. If the boot mode is SD card, the BootROM lockdowns the system and generates an
error code.
Encryption Status — 0x028
Encryption Status determines if the boot is secure (the boot image is encrypted) or non-secure
mode. Valid values for this field are:
•
0xA5C3C5A3 Encrypted FSBL/User code (requires eFUSE key source).
•
0x3A5C3C5A Encrypted FSBL/User code (requires battery-backed RAM key source).
•Not
0xA5C3C5A3 or 0x3A5C3C5A. Non-encrypted FSBL/User code (no key).
The eFuse states and the encryption status word determines the source of the encryption key, if any.
The valid combination are shown in Table 6-6.
FSBL/User Defined — 0x02C
This word may be used by the FSBL or User code. Refer to UG821, Zynq-7000 All Programmable SoC
Software Developers Guide for more information. The BootROM does not interpret or use this field.
Source Offset — 0x030
This parameter contains the number of bytes from the beginning of the valid BootROM Header to
where the FSLB/User code image resides. This offset must be aligned to a 64-byte boundary and must be
at or above address offset
0x8C0 from the beginning of the BootROM Header.
Length of Image — 0x034
This word contains the byte count of the load image to transfer to the OCM. For non-secure mode,
the Length of Image equals the Total Image Length parameter and has a maximum value of 192 KB.
For secure mode, the Length of Image is set equal to the length of the image after it has gone
through the authentication and decryption process steps. In this case, the Length of Image is always
less than 192 KB because of the encryption overhead.
A value of zero with a Quad-SPI or NOR flash mode causes the BootROM to execute the FSBL/User
code from the associated flash device without copying the image to OCM (execute-in-place).
Table 6-6: BootROM Requirements for Encryption Status Word
eFuse States (described in Table 32-2, page 771)
eFuse Secure Boot
Not Blown Not Blown Blown
BBRAM Key Disable
Not Blown Blown Don’t Care
Encryption Status Word
Non-secure
Okay Okay Lockdown
Secure with BBRAM Key
Okay Lockdown Lockdown
Secure with eFuse Key
Okay Okay Okay