User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 174
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
are commonly used to optimize the boot device interface and set its clock frequency to maximize
performance. These register writes are done toward the end of the BootROM execution.
A register initialization pair appears as two 32-bit words, first a register address, then a register write
value. Register initializations can be in any order, and the same register can be initialized with
different values as many times as desired. The register initialization is performed prior to copying the
FSBL/User code so the user can modify the default reset register values to reduce the time to access
the code and process it.
The BootROM stops processing the Register Initialization list when either the address register =
0xFFFF_FFFF or the end of the list (256 address/write data pairs).
Usage of the register initialization parameters are explained in the “Register Initialization to Optimize
Boot Times” section of section 6.3.3 BootROM Performance.
Restricted Addresses
The register address space for the Register Initialization address-data writes is restricted. Register
addresses outside of the allowed address range cause the BootROM to lockdown the system and
generate error code
0x2111. The allowed register accesses depend on the boot mode and are listed
in Table 6-7.
These restrictions are enforced by the BootROM. They do not apply when the FSBL/User code begins
to execute. The BootROM screens the register initialization writes and disallows certain addresses
from being accessed.
Table 6-7: BootROM Accessible Address Ranges for Register Initialization
Control Registers
Non-Secure Boot Mode
Secure Boot Mode
Ranges Exceptions to Range
(1)
UART 1 E000_1000 to E000_1FFC ~No
Quad-SPI E000_D000 to E000_DFFC ~No
SMC E000_E000 to E000_EFFC ~No
SDIO 0 E010_0004 to E010_0FFC E010_0058 No
DDR Memory F800_6000 to F800_6FFC ~No
SLCR registers
PLL, Peripheral, AMBA and
CPU clock controls
F800_0100 to F800_0234
Reserved: F800_01B0
PS Reset Ctrl: F800_0200
PLL, Peripheral and PL clock
controls:
F800_0100 to F800_01AC
SWDT Reset F800_024C ~
SWDT clock,
TZ configuration,
PS ID code,
DDR configuration,
MIO pins, SD card WP/CD
routing
F800_0304 to F800_0834 ~
Reserved F800_0A00 to F800_0A8C ~
Reserved, GPIO and DDR I/O
controls
F800_0AB0 to F800_0B74 ~