User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 175
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
FSBL/User Defined — 0x8A0 - 0x8BF
This memory area may be used by the FSBL or User code. Refer to UG821, Zynq-7000 All
Programmable SoC Software Developers Guide for more information.
FSBL Image or User Code Start Address — 0x8C0
The FSBL Image or User Code must start at or above this location. The location is pointed to by the
Source Offset parameter and must be aligned to 64 bytes.
6.3.3 BootROM Performance
The BootROM performance is an important factor to the total bring-up time of the system that
includes: Power-up, BootROM execution, FSBL/User code execution, U-boot time, and OS loading
time. The entire boot and configuration process is explained in section 6.4 Device Boot and PL
Configuration.
Below are a few topics related to BootROM execution that include using the Register Initialization
mechanism in the BootROM Header to optimize the bandwidth of the flash device interface. The
flash device bandwidth is the single most important factor in speeding up boot times.
Typical BootROM Execution
The BootROM time is measured from when the system powers-up to when the BootROM branches to
the FSBL/User code:
1. PS Power-up time, see table in section 6.5 Reference Section.
2. PS PLL lock time, see PS PLL Lock Time.
3. BootROM CRC check of ROM code (if enabled).
4. PL ready time (T
POR
) required when the PL is required:
°
Voltage ramp-up – time depends on the power supply performance.
°
PL Cleaning – time depends on the size of the device.
5. BootROM Header register initialization writes to optimize the flash device interface bandwidth.
6. BootROM normally copies FSBL/User code to OCM memory and optionally performs decryption
and authentication:
UART 0, USB, I2C, SPI, CAN,
GPIO, GigE, TTC, DMAC,
SWDT, DDR, DevC, AXI HP
Not accessible Not accessible
Notes:
1. The registers in this column are not accessible by the Register Initialization writes.
Table 6-7: BootROM Accessible Address Ranges for Register Initialization (Cont’d)
Control Registers
Non-Secure Boot Mode
Secure Boot Mode
Ranges Exceptions to Range
(1)