User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 176
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
°
BootROM RSA authentication, if enabled by eFuse.
°
BootROM AES/SHA decryption/authentication (secure boot).
7. BootROM branches to FSBL/User code.
Start-up details and PL configuration information is provided in section 6.4 Device Boot and PL
Configuration.
PS PLL Lock Time
The PLL is enabled by a pin strap. If the PLL is in bypass mode and then enabled by PS software, the
PLL with take some time to lock. The length of time is specified by the t
LOCK_PSPLL
parameter in the
data sheet. The programming of the PLLs are described in section 25.10.4 PLLs. Also refer to section
6.5 Reference Section. The length of the PLL lock time varies, but it is relatively small compared to
the other boot stages.
Register Initialization to Optimize Boot Times
The clocking and I/O configuration can be modified before the FSBL/User code is accessed by using
the register initialization parameters in the BootROM Header. These settings can be matched to the
specific device used and the board layout. Register initialization takes a negligible amount of time,
but can have a drastic effect on performance while copying the FSLB/User code to the OCM memory
or routing it to the decryption unit in the PL. Many of the optimizations done via register
initialization are only available in non-secure boot mode as listed in Table 6-7, page 174. Secure
mode optimizations are limited to clocking controls for the clock subsystem (not the IO controller).
There are register initialization optimization examples for each boot device:
•Quad-SPI, Table 6-10
•NAND, Table 6-12
•NOR, Table 6-14
•SD Card, Table 6-16
CRC Check for BootROM Code Option
After the power-on and hardware sequences are completed, the BootROM begins to execute.
If the OCM ROM 128 KB CRC Enable eFuse is set, then the BootROM perform a CRC on its own code
space at the beginning of the BootROM execution. Enabling the CRC check adds about 25 ms to the
BootROM time. Because the CRC check is done before the register initialization parameters are
processed, this time cannot be improved by the register initialization mechanism.
PL Considerations
When the PS and PL are powered-up together, the BootROM is delayed until PL power-on sequence
(T
POR
). This delay occurs regardless of whether the BootROM needs to use resources in the PL
voltage domain or not. If the PL is powered-up the BootROM senses this and waits for it to be
initialized.