User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 177
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
When the PL power is required, the BootROM checks to determine if the PL is powered on before
accessing modules in the PL. If the PL is powered-up, then it checks to see if the PL clearing process
completed. It waits up to 90 seconds (PS_CLK = 60 MHz) for the process to be done. A slower PS_CLK
frequency means the BootROM will wait longer than the 90 seconds. If the PL is not cleared by this
time, then the BootROM locks down the system and generate an error code. After the PL is cleared,
the BootROM initializes the PL so it is ready for the bitstream that is loaded by the FSBL/User code.
PL Power-on Reset Time (TPOR)
T
POR
is the PL voltage ramp time and it is important to the boot time when PL power is required for
the boot process and it is not already powered-up. PL power is needed in the situations listed in
Table 6-1, page 161.
In a normal cold power-up, the PS and PL power supplies come up together so there can be some
overlap of activities.
If the PL is already powered on when the BootROM needs it, then T
POR
is not a factor. Refer to the
appropriate data sheet, DS187 or DS191 for times. The power-on timing is also discussed in
A
R# 55572.
In a non-secure boot, when both the PS and the PL are powered on, the BootROM does not wait for
the T
POR
time. The BootROM loads the FSBL/User code into the OCM, and the FSBL starts configuring
the PS. Before the PL bitstream is loaded, you might have to wait up to 50 ms for the PL to be ready
after it is powered on. To ensure the PL is ready, the user code can check the devcfg.STATUS
[PCFG_INIT] bit before programming the bitstream. For details, see section 6.5 Reference Section.
In secure boot mode, the AES and HMAC units in the PL is used for decryption and authentication of
the FSBL. If the board is being powered up for the first time, the BootROM waits for the PL to be
ready, which includes the T
POR
for the PL. If the board was already powered up and only the device
is being reset, then because the PL was already powered on and voltage ramp has already taken
place, the T
POR
parameter is not a factor in the PL bring-up time. In this case, you only have to wait
for the PL initialization time, which is device dependent.
PS_POR_B De-assertion Guidelines
To prevent security attacks from tampering with the PL power supply voltage, the BootROM checks
for PL power stability by sampling power status multiple times. Any change in PL power supply seen
at the sampling points is treated as a security attack on the device and the PS enters secure lock
down. To prevent secure lock down from occurring in a system, the user needs to ensure that the PL
power is stable before the bootROM checks for its stability. This can be achieved by controlling the
timing relationship between de-assertion of PS_POR_B with respect to the last PL power supply
starting to ramp.The timing window that defines the above relationship (Secure Lock Down window)
is influenced by the following design parameters:
•PS_CLK frequency
• PLL bypass mode
• Efuse CRC 128K enable
• PL power supply ramp rate
• Device size