User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 178
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
A timing window calculator that also takes into account PVT variations provides a quick way to assess
if the design is exposed to the risk of a secure lock down as described above. The calculator is
available through AR# 63149
. PS_POR_B must be de-asserted outside the Secure Lock Down window
shown in the calculator to avoid the risk.
Note: Tslw(min) and Tslw(max) values can be negative in some cases. This indicates that PS_POR_B
needs to be de-asserted before the last PL power supply starts to ramp.
AES Decryption and HMAC Authentication
AES decryption requires the image to be accessed by DMA through the PCAP interface and then be
written to OCM memory. HMAC authentication requires another pass through the PCAP interface to
access the HMAC unit.
RSA Authentication Time
The BootROM can authenticate a secure or non-secure FSBL prior to execution using the RSA public
key authentication. This feature is enabled by triggering the RSA Authentication Enable fuse in the
eFuse array.
The RSA authentication time takes about 56 ms for a 128 KB FSBL using a 33.33 MHz PS_CLK, and
default register settings (that is, the CPU divider value 4). Under these conditions, the CPU runs at
215 MHz. The CPU divider value can be changed to divide by 2 by the register initialization
parameters. This cuts the authentication time in half (28 ms) because the CPU runs at 433 MHz.
BootROM and Image Copy Time
The image copy time and execute time vary greatly depending on the configuration of the boot
interface. Table 6-8 lists the BootROM times for the primary boot modes with default and optimized
register values. All values assume a 33.33 MHz PS_CLK clock and are for a 128 KB FSBL/User code
image size.
The boot times in Table 6-8 include the time from the deassertion of the PS_POR_B signal until the
BootROM branches to the FSBL image copied into the OCM. This includes PLL lock time, BootROM
execution time, PL initialization time, and the time to copy the FSBL to the OCM. For secure boot, it
also includes the time to decrypt and authenticate the FSBL through the AES/SHA unit. The PL T
POR
,
Table 6-8: BootROM Times for the Master Boot Modes
Boot Mode
Non-Secure Boot Secure Boot
Default Regs (ms) Reg-Init (ms) Default Regs (ms) Reg- Init (ms)
Quad-SPI (4-bit) 98.4 16 100 24
Quad-SPI (8-bit)72127420
NAND x81145212060
NAND x1692509256
NOR72127222
SD card 216 196 216 204