User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 179
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
RSA authentication time, or the time for the 128 KB CRC check on the BootROM is not included. The
PL T
POR
time includes power-up and internal hardware sequencing.
6.3.4 Quad-SPI Boot
Quad-SPI boot has these features:
• x1, x2, and x4 single device configuration.
• Dual SS, 8-bit parallel I/O device configuration.
• Dual SS, 4-bit stacked I/O configuration.
• Execute-in-place option.
RECOMMENDED: For details on the specific devices that Xilinx recommends for each boot interface,
refer to AR# 50991.
Note: The dual SS, 4-bit stacked I/O device configuration is supported, but the BootROM only
searches within the first 16 MB address range. The BootROM accesses the device connected to the
QSPI0_SS_B slave select signal.
Note: In cases of Quad-SPI boot, if the image is authenticated, then the boot image should be
placed at a 32K offset other than
0x0 (the image should not be placed starting at 0x0 offset in
Quad-SPI).
Note: There are special reset requirements when using more than 16 MBs of Flash memory. For
hardware, please refer to AR# 57744
for information. For software considerations, refer to UG821,
Zynq-7000 All Programmable SoC Software Developers Guide.
I/O Configuration Detection
The BootROM can detect the intended I/O width of the Quad-SPI interface using the Width
Detection (
0xAA995566) parameter value and, in the 8-bit parallel case, also using the Image
Identification (
0x584C4E58) parameter value.
4-bit I/O Detection
During the Quad-SPI boot process, the BootROM configures the controller with 4-bit I/O. This
configuration includes a single device and the dual 4-bit stacked case. The BootROM reads the first
(and, perhaps, only) Quad-SPI device in x1 mode. It reads the Width Detection parameter in the
BootROM Header. If the Width Detection parameter is equal to
0xAA995566, then the BootROM
assumes it found a valid header that is requesting a 4-bit I/O configuration. It might be one device
or it might be a dual 4-bit stacked configuration. In the latter case, the second device is always
ignored by the BootROM, but it might be accessed by user code. After reading the Width Detection
parameter in x1 mode, the BootROM attempts to read the parameter in x4 mode. If x4 mode fails, it
tries x2 mode. After this, the BootROM uses the widest supported I/O bus width to access the
Quad-SPI device.
8-bit I/O Detection
The BootROM also looks for the dual device, 8-bit parallel configuration. In this case, the BootROM
only reads the even bits of the BootROM Header because it is only accessing the first device and the