User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 180
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
header is split across both devices. The BootROM forms a 32-bit word that includes the even bits of
the Width Detection (
0x20) and Image Identification (0x24) parameter values. When the BootROM
detects this condition, it assumes the system uses the 8-bit parallel configuration and programs the
controller for the x8 operating mode. This mode is used for the rest of the boot process. The
Quad-SPI I/O configurations are shown in section 12.5 I/O Interface.
BootROM Header Search
If the BootROM does not detect a valid header, then the BootROM searches until one is found or the
32 MB search limit is reached. In the 4-bit stacked I/O case, only the first Quad-SPI device is searched
and the search is limited to the first 16 MB of memory. The BootROM Header search is described in
section 6.3.10 BootROM Header Search.
MIO Programming
The values loaded in to MIO_PIN registers during the Quad-SPI boot mode process are shown in
Table 6-9. Initially, the BootROM enables 4-bit mode. If the width detection mechanism determines
an 8-bit data width, then additional MIO pins are enabled as shown in the table.
Table 6-9: Quad-SPI Boot MIO Register Settings
Quad-SPI
I/O Interface
Signal Name
MIO Pin
Number
MIO_PIN
Register
Setting
(1)
Pin State
I/O
I/O Buffer
Output, Pull-up
External
Connection
Quad-SPI Boot
QSPI_CS0 MIO 1 0x0602 OEnabled ~
QSPI_IO[0:3] MIO 2 to 5 0x0602 I/O Enabled Pull up/down
QSPI_SCLK0 MIO 6 0x0602 O Enabled Pull up/down
not Quad-SPI MIO 7 0x0601 I 3-state Pull up/down
QSPI_SCLK_FB_OUT
(not used for boot)
MIO 8 0x0601 I 3-state Pull up/down
not Quad-SPI MIO 14 to 53 0x1601 I 3-state ~
4-bit Quad-SPI Boot
QSPI_CS1 MIO 0 0x1601 I 3-state ~
QSPI_SCLK1 MIO 9 0x1601 I 3-state ~
QSPI_IO[4:7] MIO 10 to 13 0x1601 I 3-state ~
8-bit Quad-SPI Boot
QSPI_CS1 MIO 0 0x0602 OEnabled ~
QSPI_SCLK1 MIO 9 0x0602 OEnabled ~
QSPI_IO[4:7] MIO 10 to 13 0x1602 I/O Enabled, Pull-up ~
Notes:
1. These register settings are for LVCMOS25/33. Change the 6 to a 2 for LVCMOS18 (bits 11:9 change from
011 to 001).