User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 181
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
Execute-in-Place Option
For the execute-in-place option, the BootROM uses the linear addressing feature of the Quad-SPI
controller for non-secure boot modes. In this case, the initial FSBL/User code must fit inside the first
16 MB of memory for a single device and 32 MB of memory for a x8 dual Quad-SPI device system.
Configuration Register Settings
The BootROM sets qspi.LQSPI_CFG to use these settings:
•CLK_POL:
0, CLK_PH: 0
• BAUD_RATE_DIV: 1 (by 4)
•INST_CODE is set as:
°
x1 mode = 0x03, x2 mode =0x3B, x4 mode = 0x6B
• DUMMY_BYTE is set as:
°
x1 mode= 0, x2 and x4 mode = 1
• SEP_BUS and TWO_MEM are set if a dual x4 configuration is used
Boot Time Optimizations
The Quad-SPI boot process can be sped up by modifying the operating mode before the process to
read the flash contents into OCM begins. You program the BootROM Header Register Initialization
parameters to improve boot times or select modes. The Register Initialization parameters are
explained at the end of section 6.3.2 BootROM Header.
The optimized values for the registers in the following examples are obtained from vendor data
sheets. The following examples show the settings for the Quad-SPI interface. These are examples;
they might not be optimized for a specific flash device or board design. The settings assume a 33
MHz PS_CLK. If a faster clock is used, then a larger divider must be considered.
The optimizations for the MIO multiplexer, clock controls and other configurations are shown in
Table 6-10. If the width or security combination is not listed for a register, then the post BootROM
value is used.
Table 6-10: Quad-SPI Boot Time Optimization Register Setting Examples
Register Width Security
(2)
Register
Value
Description
slcr.ARM_CLK_CTRL All Both
0x1F000200
CPU divisor = 2 (433 MHz)
slcr.MIO_PIN_08 All Non-secure
0x00000602
Feedback clock, 3.3V
slcr.LQSPI_CLK_CTRL
All Non-secure
0x00000521
Controller divisor = 5 (173 MHz)
All Secure
0x00000621
Controller divisor = 6 (144 MHz)
qspi.Config_reg All Non-secure
0x800238C1
Baud rate divide-by-2 (86 MHz)
qspi.LPBK_DLY_ADJ All Non-secure
0x00000020
Clock Loopback, 0 delay