User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 182
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
6.3.5 NAND Boot
NAND boot has these features:
• 8-bit or 16-bit NAND flash devices
• Supports ONFI 1.0 device protocol
• Bad block support
• 1-bit hardware ECC support
The boot image must be located within the first 128 MB address space of the NAND flash device for
the BootROM Header search function.
Note: The BootROM reads the ONFI compliant parameter information in 8-bit mode to determine
the device width. If the device is 16 bits wide, then the BootROM enables the upper eight I/O signals
for a 16-bit data bus. The 16-bit NAND interface is not available in 7z010 dual core and 7z007s single
core CLG225 devices.
RECOMMENDED: For details on the specific devices that Xilinx recommends for each boot interface,
refer to AR# 50991.
The MIO pin programming for 8- and 16-bit boot modes are listed in Table 6-11.
qspi.LQSPI_CFG All Non-secure
(1)
Device Configuration
1. The qspi.LQSPI_CFG register value depends on the type of device, the interface width and the number of devices
attached. Optimized values for the qspi.LQSPI_CFG register are shown in Table 12-3, page 344.
2. In secure mode, the qspi and slcr.MIO_PIN registers are not accessible for optimization using the Register
Initialization writes as shown in Table 6-7.
Table 6-10: Quad-SPI Boot Time Optimization Register Setting Examples (Cont’d)
Register Width Security
(2)
Register
Value
Description
Table 6-11: NAND Boot MIO Register Settings
NAND Flash
I/O Interface
Signal Name
(SMC controller)
MIO Pin
Number
MIO_PIN
Register
Setting
(1)
Pin State
I/O
I/O Buffer
Output, Pull-up
External
Connection
NAND Boot
NAND_CE_B MIO 0 0x0610 I/O Enabled
non NAND MIO 1 0x1601 I 3-state ~
NAND_ALE MIO 2 0x0610 O Enabled Pull-up/down
NAND_WE_B MIO 3 0x0610 O Enabled Pull-up/down
NAND_IO[2] MIO 4 0x0610 I/O Enabled Pull-up/down
NAND_IO[0] MIO 5 0x0610 I/O Enabled Pull-up/down
NAND_IO[1] MIO 6 0x0610 I/O Enabled Pull-up/down
NAND_CLE MIO 7 0x0610 O Enabled Pull-up/down
NAND_RE_B MIO 8 0x0610 O Enabled Pull-up/down