User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1859
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
Register ENDPTCTRL0 Details
Every device controller implements Endpoint 0 as a control endpoint.
Rx and Tx Endpoint Stall bits [0] and [16]:
Software can write a one to a stall bit to force the endpoint to return a STALL handshake to the Host. The
device controller will continue returning STALL until the bit is cleared by software or it will automatically
be cleared upon receipt of a new SETUP request. After receiving a SETUP request, the stall bit will continue
to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Note: There is a slight
delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear
this bit. In most systems it is unlikely the software will observe this delay. However, should the software
observe that the stall bit is not set after writing a 1 to it then follow this procedure: continually write this
stall bit until it is set or until a new SETUP has been received by checking the associated
ENDPTSETUPSTAT bit.
Absolute Address usb0: 0xE00021C0
usb1: 0xE00031C0
Width 24 bits
Access Type mixed
Reset Value 0x00800080
Description Endpoint 0 (Device mode)
Field Name Bits Type Reset Value Description
TXE
(EPCR_TXE)
23 ro 0x1 Transmit Endpoint Enable, read-only.
1: EP 0 is always enabled.
reserved 22:20 ro 0x0 reserved
TXT
(EPCR_TXT_INTR)
19:18 ro 0x0 TX Endpoint Type, read-only.
00: EP 0 is always a control endpoint.
reserved 17 ro 0x0 reserved
TXS
(EPCR_TXS)
16 rw 0x0 TX Endpoint Stall, read-only.
0: Normal operation.
1: Force Stall handshake.
Note: refer to the register description for more
description.
reserved 15:8 ro 0x0 reserved
RXE
(EPCR_RXE)
7 ro 0x1 RX Endpoint Enable, read-only.
1: EP 0
is always enabled.
reserved 6:4 ro 0x0 reserved
RXT
(EPCR_RXT_INTR)
3:2 ro 0x0 RX Endpoint Type, read-only.
00: EP0 is always a control endpoint.