User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 186
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
The BootROM uses the following NOR timing values in the smc.SET_CYCLES register:
• we_n asserts 2 clocks after cs_n, t_ta=1, t_pc=2, t_wp=5, t_ceoe=2, t_wc=7, t_rc=7
Boot Time Optimizations
To improve NOR boot time, raise the clock rates, and optimize the I/O protocol by setting the
registers listed in Table 6-14. The example values might not be appropriate or optimal for all NOR
devices or board layouts. The settings assume a 33 MHz PS_CLK. If a faster clock is used, then a larger
divider must be considered.
Table 6-13: NOR Boot MIO Register Settings
NOR Flash
I/O Interface
Signal Name
(SMC controller)
MIO Pin
Number
MIO_PIN
Register
Setting
(1)
Pin State
I/O
I/O Buffer
Output, Pull-up
External
Connection
SRAM_CE_B[0] MIO 0 0x0608 OEnabled ~
Not used for NOR boot MIO 1 0x1601 I 3-state ~
Not NOR/SRAM MIO 2 0x0601 I 3-state Pull-up/down
SRAM_DQ[0:3] MIO 3 to 6 0x0608 I/O Enabled Pull-up/down
SRAM_OE_B MIO 7 0x0608 O Enabled Pull-up/down
SRAM_BLS_B MIO 8 0x0640 O Enabled Pull-up/down
SRAM_DQ[6:7] MIO 9 to 10 0x1608 I/O Enabled, pull-up ~
SRAM_DQ4 MIO 11 0x1608 I/O Enabled, pull-up ~
Not NOR/SRAM MIO 12 0x0608 I 3-state ~
SRAM_DQ5 MIO 13 0x1608 I/O Enabled, pull-up ~
Not NOR/SRAM MIO 14 0x1601 I 3-state ~
SRAM_A[0:24] MIO 15 to 39 0x0608 OEnabled ~
Not NOR/SRAM MIO 40 to 53 0x1601 I 3-state ~
Notes:
1. These register settings are for LVCMOS25/33. Change the 6 to a 2 for LVCMOS18 (bits 11:9 change from
011 to 001).
Table 6-14: NOR Boot Time Optimization Register Setting Example
Register Security Value Description
slcr.ARM_CLK_CTRL both
0x1F000200
CPU divisor = 2 (433 MHz)
slcr.SMC_CLK_CTRL both
0x00000D21
Baud rate divisor = 13 (66 MHz, 15 ns)
smc.set_cycles Non-secure
0x0002AA77
Timing Parameters:
we_n asserts 2 clocks after cs_n, t_ta=1,
t_pc=2, t_wp=5, t_ceoe=2, t_wc=7, t_rc=7
smc.set_opmode Non-secure
0x00000110
32-beat bursts, 8-bit width
smc.direct_cmd Non-secure
0x00400000
Select UpdateRegs