User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 190
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
The DAP and TAP controllers can be permanently disabled by blowing the JTAG Chain Disable eFuse.
Once the eFuse is blown, the controllers can never be accessed again. The software can read the state
of the eFuse bit using the devcfg.STATUS [EFUSE_JTAG_DIS] bit.
Note: If software attempts to unlock the APB register space in the DevC module without the proper
key, then this disables the DAP controller until the next POR reset is issued. This condition can be
detected by reading the devcfg.STATUS [ILLEGAL_APB_ACCESS] bit.
When the JTAG Boot mode is selected, the BootROM disables access to all security-related items,
enables the JTAG port, and halts the CPU by executing the WFE instruction. It is the User’s
responsibility to manage downloading the boot image into OCM or DDR memory through the DAP
controller before waking up the CPU and continuing the boot process.
Example: JTAG Boot Sequence
JTAG Boot mode is always non-secure; the AES unit is disabled and encrypted images are not
supported. The JTAG boot and PS/PL configuration flows are shown in Figure 6-7. The sequence is as:
1. PS and PL are powered-on; PS_CLK is stable.
2. PS_POR_B reset deasserts.
3. BootROM begins to execute and determines the boot mode.
4. BootROM performs CRC self-check, if enabled.
5. BootROM programs VMODE on MIO.
6. BootROM disables all security features and enables the DAP controller.
7. BootROM enables JTAG path(s):
a. Cascade: JTAG chain is set to cascade; the DAP and TAP controllers are accessible using the
PL JTAG interface.
b. Independent: JTAG chain is set to independent mode; the TAP controller is accessible via the
PL JTAG interface and the DAP controller is accessed through the EMIO JTAG. In this case, the
BootROM waits up to 90 seconds for you to program the PL (using the TAP controller) for the
EMIO JTAG connection.
8. BootROM shuts down and leaves CPUs running the wait for event (WFE) instruction:
a. Cascade: BootROM shuts down and releases system control to the JTAG interface for the TAP
and DAP controllers.
Table 6-17: JTAG Requirements and Control
Function DAP Controller TAP Controller
Power requirements PS and PL PS and PL
PL configuration Not required
Not required for Cascade mode.
Required for Independent mode.
devcfg.CTRL [JTAG_CHAIN_DIS] Must = 0 Must = 0
devcfg.CTRL [DAP_EN] Must = 111
Must = 111 for Cascade mode.
Don’t care for Independent mode.
APB register space is unlocked with
the wrong key
Disabled until POR reset Not affected