User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 191
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
b. Independent: BootROM waits until the PL to initialized and then shuts down. The EMIO JTAG
interface for the DAP controller must be routed through the PL using a bitstream to be
operational.
9. User can access the DAP controller for PS system debug:
a. Cascade: First device on the PL JTAG interface chain.
b. Independent: Single device on the EMIO JTAG interface chain.
10. User can access the TAP controller to configure PL:
a. Cascade: Second device on the PL JTAG interface chain.
b. Independent: Single device on the PL JTAG interface chain.
Note: For high system reliability when using the L2-cache, set the slcr.L2C_RAM register to the value
of 0x0002_0202 as explained in AR# 54190
.
Cascaded JTAG Chain Mode
The controllers are normally accessed using the cascaded JTAG chain mode. In cascade mode, both
controllers are accessed using the PL JTAG interface pins; the TDI signal from the interface goes to
the DAP controller. The TDO signal from the DAP controller is daisy chained to the TAP controller. The
TDO signal from the TAP controller go to the JTAG interface. The DAP registers and data are the last
to be shifted into the JTAG chain.
• DAP controller, then the TAP controller.
• PL configuration not required.
• Both controller must be enabled.
• Instructions and data must not adversely affect the unintended target.
Independent JTAG Chain Mode
The independent JTAG chain mode connects the TAP controller to the PL JTAG interface and provides
time for the user to use the TAP controller to configure the PL with a bitstream that routes the DAP
controller signals to the EMIO JTAG interface on the SelectIO pins as shown in Figure 6-7, page 189.
The BootROM waits up to 90 seconds for the PL configuration to complete before it enables the DAP
controller and continues with the boot process. If the PL is not configured in time, then the system
locks down.
• TAP controller is accessed through the PL JTAG pins and is used to configure the PL.
• DAP controller become accessible after the PL is configured with a bitstream.
In independent mode, the TAP controller behaves like the TAP controller in a Xilinx 7 series FPGA.
EMIO PJTAG Interface for Independent Mode
The PL must be configured with a bitstream to enable the EMIO PJTAG interface to connect to the
DAP controller. The PL can be initialized by asserting the PROGRAM_B signal and then loading the
bitstream into the PL after the DONE signal is asserted. This can be done to enable the EMIO PJTAG
interface to control the DAP controller in independent JTAG mode.