User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 192
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
Note: This functionality is only supported on production silicon and requires for the system to be
booted in independent JTAG boot mode. In this mode, the BootROM waits until the PL is self
initialized, then enables the PS-PL level shifters, enables the PL JTAG interface, and issues the WFE
instruction on the CPU.
MIO PJTAG Interface for Independent Mode
The DAP controller can interface to the MIO PJTAG interface, but it requires the FSBL/User code to
program the MIO multiplexer using the slcr.MIO_PIN_xx registers. The MIO PJTAG interface can be
routed to one of four sets of MIO pins as shown in Table 2-4, page 52. PL power is not required for
the MIO PJTAG interface and DAP controller to be used.
The TAP controller cannot program the MIO multiplexer. You must boot from a flash device that
includes FSBL/User code that configures the MIO multiplexer for the MIO PJTAG interface. After the
MIO multiplexer is programmed, the DAP controller is accessible using the MIO PJTAG interface.
MIO Pin States for JTAG Boot Mode
The values for the MIO registers in the JTAG boot mode state are shown in Table 6-18. These values
are valid for cascade and independent JTAG boot mode.
6.3.9 Reset, Boot, and Lockdown States
Reset State
When reset is asserted (PS_POR_B or PS_SRST_B), all of the I/O pins go to a 3-state mode and all
registers are reset except those listed in Table 26-2, page 707. When reset de-asserts, then the
BootROM begins to execute to configure the PS. The default reset values for the device are shown
Appendix B, Register Details.
Boot State
The BootROM will modify MIO registers depending on the boot mode. The user can program the
Time Optimization registers using the Register Initialization parameters in the BootROM Header.
Table 6-18: MIO Pin States for JTAG Boot Mode
MIO Pin
MIO_PIN Register
Setting Value
(1)
Pin State
I/O
I/O Buffer
(GPIOB)
External
Connection
MIO pin [0:1] 0x1601 I 3-state, pull-up ~
MIO pin [2:6] 0x0601 I 3-state Pull-up/down
MIO pin [7:8] 0x0601 O 3-state Pull-up/down
MIO pin [9:53] 0x1601 I 3-state, pull-up ~
Notes:
1. These register values are based on the VMODE [0, 1] strapping pins. The register values shown are
for LVCMOS 25/33. For LVCMOS18, use:
0x1201 and 0x0201 (bits 11:9 change from 011 to
001).