User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 195
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
• An update that was started on the first image but the system was interrupted after erasing the
section requiring an update.
• The write operation began but the write process did not finish.
The BootROM Header search mechanism does not protect against:
• The memory holding the BootROM Header becoming corrupt.
• A complete header was written but it did not pass the tests. If a header is non-functional, this
might lead to a system lockdown.
The BootROM Header search does not verify the integrity of the header beyond what is listed above.
If the header indicates an invalid operation or includes instructions that contradict each other, then
the BootROM might generate a system lockdown. The lockdown error codes are listed in section
6.3.12 BootROM Error Codes.
BootROM Header Search Stepping and Range
The BootROM searches on 32-KB boundaries until a valid header is detected or the end of the range
is encountered. The header search is done for all boot devices except SD card. The search occurs
after a POR or non-POR reset including after a Multiboot operation.
The BootROM searches within a limited address space on the boot device:
•NAND: first 128MB
•NOR: first 32MB
• Quad-SPI, signal/dual SS with 4-bit I/O: first 16 MB
• Quad-SPI, dual SS with 8-bit Parallel I/O: first 32 MB
• SD card: single image in boot page, no searching
6.3.11 MultiBoot
Multiboot is a feature that allows the FSBL or User code to select the BootROM Header from multiple
images on the boot device. To select an image, the FSBL/User code writes the base memory address
location of the BootROM Header into the devcfg.MULTIBOOT_ADDR [MULTIBOOT_ADDR] bit field
and then generates a non-POR system reset. The BootROM tries to fetch the BootROM Header
located at that address. If the BootROM determines that the header is not valid, it performs a
BootROM Header search by incrementing the MULITBOOT_ADDR register until a valid header is
found or the end of the range is detected. The range depends on the boot mode and is given in the
BootROM Header Search Stepping and Range section of section 6.3.10 BootROM Header Search.
Note: In secure mode, multiboot is not supported when using an eFuse key. Fallback and multiboot
are discussed in this below and in U
G821, Zynq-7000 All Programmable SoC Software
Developer
s
Guide.