User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 198
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
Lockdown Types
The Lockdown Type column includes information based on the type of reset that started the
BootROM execution.
•POR reset (P)
•Non-POR reset (NP)
The type of lockdown indicated in Table 6-20 includes the following notations:
• Non-secure: A non-secure lockdown occurs (system can be accessed by JTAG).
• Header: The lockdown type is defined by the Encryption Status parameter in the header.
• Secure: Always a secure lockdown (the system becomes inaccessible).
• Previous: Applies only after a non-POR reset. If the previous boot mode was secure, then this
subsequent lockdown is secure. If the previous boot was non-secure, then this subsequent
lockdown is non-secure.
Table 6-20: BootROM Error Codes
Error
Code
Lockdown
Type
(1)
Description Solution
0x0002
P: Non-secure
NP: Non-secure
The system successfully booted in JTAG
mode.
• Use the JTAG interface to the DAP and
TAP controllers.
0x2000
P: Non-secure
NP: Previous
Quad-SPI boot mode. The BootROM
detected a x8 parallel device configuration
using x1 mode, but then failed to read the
expected header parameters using x8 mode.
The BootROM continues with header search
using x8 mode, but it was unable to find the
Width Detection word using header search
within the image search range.
• Check that the Quad-SPI device is
properly connected to the QSPI MIO
pins.
• Be sure that the Width Detection word is
set equal to the data pattern
0xAA995566 and that the Image
Identification word has 0x584C4E58,
‘XLNX’
0x2001
P: Non-secure
NP: Previous
NAND boot mode. The BootROM could not
determine the ECC mode for the device.
• Check that the NAND device is on the
vendor approved list, refer to (Xilinx AR#
50991).
0x200A
P: Non-secure
NP: Previous
SD card boot mode. The BootROM could not
find the boot image at the root of the SD
card; only a single boot image is supported
for this boot mode.
If the SD card was accessed by the FSBL/User
code and then a system reset occurs without
resetting the SD card, then the SD card
might be left in 4-byte addressing mode.
• Check that there is a valid BootROM
Header in the root directory of the SD
card named BOOT.BIN.
• Make sure the SD interface is operating
reliably; for example using XMD or other
debug tool to access it.
• Make sure the SD card is in 3-byte
addressing mode.
• Check the mode pin settings.
0x200B
P: Non-secure
NP: Previous
NOR boot mode. The BootROM could not
find a valid boot image in the NOR device
after searching.
• Check that there is a valid BootROM
Header within the search range, refer to
the BootROM Header Search and
Multiboot sections.
0x200C
P: Non-secure
NP: Previous
Quad-SPI boot mode. The BootROM is
unable to find a valid header within the
image search range.
• Check that there is a valid image written
within the boot partition address search
space for the device, refer to the
BootROM Header Search and Multiboot
sections.