User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 199
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
0x200D
P: Non-secure
NP: Previous
NAND boot mode. The BootROM is unable
to find a valid header within the image
search range.
• Check that there is a valid image written
within the boot partition address search
space for the device, refer to the
BootROM Header Search and Multiboot
sections.
0x200E
P: Header
NP: Previous
An address in the Register Initialization field
of the BootROM Header is out of the
accessible range.
• Check that all addresses are within the
range based on boot mode, refer to the
Register Initialization address range
table.
0x200F
P: Secure
NP: Secure
Secure boot mode. The Start of Execution
word does not equal 0.
• The Start of Execution word must be
equal to 0 in secure mode (boot from
OCM).
0x2011
P: Header
NP: Previous
NAND boot mode. Length of Image
parameter is = 0. The execute-in-place mode
is not supported in the NAND boot mode.
• Set the Length of Image parameter to
the length of the boot image. Must fit
into the 192 KB of available OCM
memory.
0x2012
P: Header
NP: Previous
SD card boot mode. Length of Image
parameter is = 0. The execute-in-place mode
is not supported in the SD card boot mode.
• Set the Length of Image parameter to
the length of the boot image. Must fit
into the 192 KB of available OCM
memory.
0x2019
P: Secure
NP: Secure
The encryption and eFuse combinations are
not valid, refer to Table 6-7.
•Make sure the Encryption Status
parameter and the eFuse states are
consistent.
0x201A
P: Secure
NP: Secure
Security Violation was detected. The system
tried to transition from a secure operating
mode to a non-secure boot mode without
using POR.
• Assert the POR reset to boot in
non-secure mode when the system was
previously booted in secure mode.
0x2023
P: Non-secure
NP: Previous
There is a mismatch between the value in the
Header Checksum word and the calculated
checksum for the header, or the Image
Identification word in the BootROM Header
does not contain 0x584C4E58,'XLNX'.
• Verify that the Header Checksum is
correct.
• Make sure the Image Identification word
has 0x584C4E58.
• Verify that the boot device can be
accessed reliably using the JTAG boot
mode.
0x2024
P: Header
NP: Previous
The Image Identification word in the
BootROM Header does not contain
0x584C4E58, 'XLNX'.
• Make sure the Image Identification word
equals 0x584C4E58.
• Verify that the boot device can be
accessed reliably using the JTAG boot
mode.
0x21
00
P: Non-secure
NP: Previous
The Image Identification word in the
BootROM Header does not equal
0x584C4E58, 'XLNX'.
• Make sure the Image Identification word
has 0x584C4E58.
• Verify that the boot device can be
accessed reliably. Boot in JTAG mode and
test, if necessary.
0x2101
P: Non-secure
NP: Previous
BootROM Header checksum fails.
• Verify that the Header Checksum is
correct.
• Verify that the boot device can be
accessed reliably using the JTAG boot
mode.
Table 6-20: BootROM Error Codes (Cont’d)
Error
Code
Lockdown
Type
(1)
Description Solution