User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 200
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
0x2102
P: Non-secure
NP: Previous
The address value in the Source Offset word
points to a location within the BootROM
Header instead of where the image is
actually located.
• Check the address value in the Source
Offset word.
0x2103
P: Non-secure
NP: Previous
The address value in the Source Offset word
is not aligned to a 64B boundary.
• Align the address in the Source Offset
word to a 64-byte boundary.
0x2106
P: Non-secure
NP: Previous
Non-secure and execute from OCM mode.
The Length of Image parameter exceeds the
192 KB limit of the OCM for the initial
FSBL/User code.
• Reduce the size of the initial FSBL/User
code that is loaded into the OCM.
0x2108
P: Non-secure
NP: Previous
Non-secure and execute from OCM mode.
The Start of Execution parameter is greater
than 192 KB (0x03 0000).
• The Start of Execution value must be
within the OCM.
0x2109
P: Non-secure
NP: Previous
The Reserved parameter (0x038) is not set =
0.
• Set the reserved parameter at 0x038 to
0.
0x210A
P: Non-secure
NP: Previous
Applies to secure boot mode. The Length of
Image word in the header is set to 0
(execute-in-place).
• Execute-in-place is not supported in
secure mode. Either specify non-secure
mode, or change the Length of Image
word to match the image length after
decryption.
0x210B
P: Secure
NP: Previous
Secure mode. HMAC error occurred.
• Verify that the key and key source are the
same for encryption and decryption.
0x210D
P: Header
NP: Previous
This error occurs if the image length is not
equal to 0 and the length is greater than
192 KB.
• Reduce the size of the initial FSBL/User
code that is loaded into the OCM.
0x210E
P: Header
NP: Previous
The Length of Image parameter is set to 0
indicating an execute-in-place boot, but the
selected boot mode does not support
execute-in-place.
• Check the boot mode settings.
• NAND and SD card do not support
execute-in-place.
0x210F
P: Header
NP: Previous
BootROM Header checksum failed before
processing the Register Initialization words.
• Verify that the Header Checksum is
correct.
• Verify that the boot device can be
accessed reliably using the JTAG boot
mode.
0x2110
P: Header
NP: Previous
The Image Identification word in the
BootROM Header does not contain
0x584C4E58, 'XLNX'.
•
Make sure the Image Identification word
has 0x584C4E58.
• Verify that the boot device can be
accessed reliably by using the JTAG boot
mode to download test software.
0x2111
P: Header
NP: Previous
One or more address/write-data pairs in the
Register Initialization section of the
BootROM contains an address outside of the
allowed range.
• Make sure the addresses in the Register
Initialization section are within the
ranges defined in the TRM table 6-13
Boot Image Address-Data Write Address
Ranges.
Table 6-20: BootROM Error Codes (Cont’d)
Error
Code
Lockdown
Type
(1)
Description Solution