User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 206
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
Low until the [PCFG_PROG_B] bit is set High by the hardware. The programming sequence to
initialize the PL include these steps:
1. Set [PCFG_PROG_B] signal to High
2. Set [PCFG_PROG_B] signal to Low
3. Poll the [PCAP_INIT] status for Reset
4. Set [PCFG_PROG_B] signal to High
5. Poll the [PCAP_INIT] status for Set
PL Configuration via PS Software
PL configuration and reconfiguration support are illustrated with an example that simplifies software
knowledge of state. The sequence assumes the PL is uninitialized and system state is unknown. Users
can build on these steps.
To configure the PL, enable the interface and select the PCAP programming path. Clear interrupts,
initialize the PL, and disable the internal DevC loopback function. The new bitstream is transferred to
the PL using the DevC DMA unit. Both the PS and PL must be powered on to configure or reconfigure
the PL.
6.4.2 Boot Sequence Examples
There are a multitude of variables in the boot process of the PS and PL. An entire boot sequence can
include PS and PL hardware operations, BootROM execution, FSBL/User code execution and starting
the operating system software.
When considering a secure environment, there are multiple resources to reference. At the low-level,
refer to this chapter and Chapter 32, Device Secure Boot. As the system transitions to the FSBL and
the Operating System, refer to UG821
, Zynq-7000 All Programmable SoC Software Developers Guide.
The fastest boot times are obtained in PS-only non-secure mode. For time critical applications, there
are several areas to consider. Major time sinks for time critical applications include the bandwidth of
the boot device, decryption, power supply ramp time, and the ROM code CRC check.
IMPORTANT: The time it takes for each boot process to complete can be difficult to calculate because
of all the variables involved. The values provided here are meant as a guide, not a definitive answer. If
you have any questions, please contact your Xilinx FAE Sales Engineer.
This section starts by defining a few different boot sequences that are controlled by PS software
(BootROM or FSBL/User code).
Example Sequences
• Seq 1: PS Non-secure Bring-up (no PL power)
•Seq 2: PS Secure Bring-up with PL Configuration
• Seq 3: PL Bring-up by FSBL/User Code