User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 210
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
Example: Configure the PL via PCAP Bridge
1. Enable the PCAP bridge and select PCAP for reconfiguration. Write ones to devcfg.CTRL
[PCAP_MODE] and [PCAP_PR] bits.
2. Clear the Interrupts. Write all ones to the devcfg.INT_STS register.
3. Initialize the PL (clears previous configuration):
a. Set devcfg.CTRL [PCFG_PROG_B] bit = 1.
b. Set [PCFG_PROG_B] bit = 0.
c. Wait for devcfg.STATUS [PCFG_INIT] bit = 0.
d. Set [PCFG_PROG_B] bit = 1.
e. Wait for [PCAP_INIT] bit = 1.
X-Ref Target - Figure 6-16
Figure 6-16: PL Bring-up by FSBL/User Code Example
3/
7
325
3/,QLW
(QDEOH
3&$3
8*BFBEB
>3&)*B,1,7@
>3&)*B352*B%@
'21(
2'2XWSXW
WRPV
QRWH
QRWH QRWH
127()LJXUHQRWWRVFDOH
3/SRZHU
3RZHUXS
>3&)*B325B%@
,1,7B%
2'2XWSXW
3&)*B'21(B,17
,QWHUUXSWWR*,&
1RWH7KHWZRRSHQGUDLQ2'RXWSXWVLJQDOVDUHREVHUYDEOHWRWKHXVHU
EXWERDUGORJLFPXVWQRWGULYHWKHPORZZKLOHWKH36LVLQFRQWURORIWKH3/
LQLWLDOL]DWLRQDQGFRQILJXUDWLRQ
5HDG
:ULWH
5HDG
6HTXHQFH
3/%ULQJXSE\)6%/8VHU&RGH
3/LV&RQILJXUHG
>3&)*B'21(B,17@
5HDG
)6%/,QLWLDOL]HG3/SULRUWR
3/&RQILJXUDWLRQ
WRJJOHV>3&)*B352*B%@ELW
&RQILJXUHWKH3/
6HHQRWH
&RQILJXUH3/
ZLWKD%LWVWUHDP
QRWH
(QDEOH
3/
QRWH
1) PL T
POR
Time. The T
POR
time is dependent on the voltage ramp of the power supply. The allowed PL voltage
ramp time and T
POR
times are specified in the data sheet. If the PL is already powered-up, then T
POR
time = 0.
2) PL Init Time. The PL initialization time.
3) Enable PCAP. The PCAP control is described in section 6.4.3 PCAP Bridge to PL.
4) Configure the PL. Loading the PL Bitstream depends on many factors, see Table 6-25, page 221.
5) Enabled. The PL is in user mode when the [PCFG_DONE_INT] bit reads a 1. There is an example PL enable
sequence in section 2.4 PS–PL Voltage Level Shifter Enables.