User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 211
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
4. Check that there is room in the Command Queue. Verify devcfg.STATUS [DMA_CMD_Q_F] = 0.
Note, this step is not necessary if the PL is in the initialized state.
5. Disable the PCAP loopback. Write a zero (
0) to the devcfg.MCTRL [INT_PCAP_LPBK] bit.
6. Program the PCAP_2x clock divider.
a. Secure Mode: Set devcfg.CTRL [QUARTER_PCAP_RATE_EN] bit = 1.
b. Non-secure Mode: Clear [QUARTER_PCAP_RATE_EN] bit = 0.
7. Queue-up a DMA transfer using the devcfg DMA registers:
a. Source Address: Location of new PL bitstream.
b. Destination Address:
0xFFFF_FFFF.
c. Source Length: Total number of 32-bit words in the new PL bitstream.
d. Destination Length: Total number of 32-bit words in the new PL bitstream. Write to the
devcfg.DMA_DEST_LEN register last to move the value of all four registers into the Command
Queue.
8. Wait for the DMA transfer to be done. Wait for the devcfg.INT_STS [DMA_DONE_INT] bit = 1.
9. Check for errors. Interrogate bits in the devcfg.INI_STS register: AXI_WERR_INT, AXI_RTO_INT,
AXI_RERR_INT, RX_FIFO_OV_INT, DMA_CMD_ERR_INT, DMA_Q_OV_INT, P2D_LEN_ERR_INT,
PCFG_HMAC_ERR_INT.
10. Make sure the PL configuration is done. Poll for [PCFG_DONE_INT] bit = 1.
If the PL is cleared using devcfg.CTRL [PCFG_PROG_B], then the devcfg.INT_STS [PCFG_DONE_INT]
bit is set when the PL is ready for reconfiguration. If the PL is cleared by asserting the PROGRAM_B
signal pin, then the DONE signal is asserted and the devcfg.INT_STS [D_P_DONE_INT] bit is set when
the operation is completed.
6.4.3 PCAP Bridge to PL
The PCAP bridge (also known as the AXI-PCAP bridge or PCAP interface) can be used to configure
the PL with a bitstream, decrypt boot images and bitstreams, and authenticate files. The bridge has
these operating modes:
• PCAP PL Bitstream Configuration Programming (encrypted and non-encrypted)
• PCAP PL Bitstream Readback
• PCAP Data Stream Decryption/Authentication
• Loopback for DMA transfers of Boot Images by BootROM and FSBL
The bridge’s DMA controller moves boot images between the FIFOs and a memory device; typically
the OCM memory, the DDR memory, or one of the linearly addressable flash devices (Quad-SPI or
NOR). The DMA controller is register programmed and can generate PS interrupts. It is a master on
the PS AXI interconnect. The bridge FIFOs normally interface with the PCAP configuration module to
transfer boot images and bitstreams.
Note: The DevC DMA controller is specifically designed for tasks associated with boot operations.
For general DMA needs, the DMA controller described in Chapter 9, DMA Controller must be used.