User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 213
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
6.4.4 PCAP Datapath Configurations
The PCAP bridge provides the FSBL/User code software with access to the PL configuration module
and decryption unit. The configuration module processes the bitstream and loads the SRAM in the
PL. The decryption unit is used to decrypt the bitstream and code files. The PL must be powered up
to use the bridge.
There are four common datapaths used with the PCAP bridge. The paths are illustrated in Figure 6-18
and Figure 6-19.
• Non-secure bitstream (unencrypted)
• Secure bitstreams and software boot images (encrypted)
• PL bitstream readback (from PL)
• Loopback for boot image transfers
Non-Secure PL Bitstream
The non-encrypted bitstream is usually accessed by DMA from the DDR memory and directly into the
PL configuration module. It bypasses the AES and HMAC units. This path can be used for
configuration and reconfiguration of the PL.
Secure Bitstreams and Software Boot Images
The encrypted bitstream is accessed by DMA from the DDR memory to the AES and HMAC units in
the PL. From the AES/HMAC units, the decrypted bitstream is routed directly to the PL configuration
module. This path can be used for configuration and reconfiguration of the PL.
There is a separate datapath and FIFO for receive and transmit in the PCAP interface bridge. This path
can be used by the FSBL/User code and operating system code.
To transfer boot images and bitstreams to the PL through the PCAP interface, the destination address
must be
0xFFFF_FFFF. Similarly, to read bitstreams from the PL through the PCAP interface, the
source address must be
0xFFFF_FFFF. Encrypted PS images must also be sent across the PCAP
interface because the AES and HMAC units reside within the PL. In this case, the DMA source address
could be an external memory interface and the destination address could be OCM memory.
Status Interrupts Bits
The DMA controller can trigger the DevC interrupt to the GIC interrupt controller upon completion
of the PL configuration transfer. The interrupt can be triggered when the AXI side of the DMA
transaction is complete (DMA_DONE_INT) or when both the AXI and PCAP transfers are complete
(D_P_DONE_INT). The AXI interconnect completion interrupt allows the software that is controlling
the DMA to perform scatter-gather type operations by issuing multiple DMA commands but holding
off the last transfer interrupt until all of the PCAP transactions are done.
Setting the two LSBs of the source and destination address to
2'b01 indicates to the DevC DMA
module the last DMA command of an overall transfer. The DMA controller uses this information to
appropriately set the DMA done interrupt. For the last DMA command, the DMA done interrupt is