User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 215
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
bitstream from the PCAP. The smallest amount of bitstream data that can be read back from the PL
is one configuration frame which contains 101 32-bit words. An example program sequence is shown
below. The datapath is illustrated in Figure 6-19.
Example: PL Bitstream Readback
This example shows the first DMA access for a PL bitstream readback:
1. DMA Source Address – location of PL readback command sequence.
2. DMA Destination Address – desired location to store readback bitstream, note that the OCM
memory is not large enough to hold a complete PL bitstream readback.
3. DMA Source Length – number of commands in the PL readback command sequence.
4. DMA Destination Length – number of readback words expected from the PL.
There are four limitations when accessing the PL configuration module:
1. Readback of configuration registers or the bitstream cannot be performed until the
devcfg.INT_STS [PCFG_DONE] bit asserts.
2. A single PCAP readback access cannot be split across multiple DMA accesses. If the readback
command sent to the PL requests 505 words, the DevC DMA must also be set up to transfer 505
words. Splitting the transaction into two DMA accesses results in data loss and unexpected DMA
behavior.
3. The DMA must have sufficient bandwidth to process the PL readback due to a lack of data flow
control on the PL side of the PCAP. Overflow of the PCAP RxFIFO results in data loss and
unrecoverable DMA behavior. If adequate bandwidth cannot be allocated to the DevC DMA, then
the PCAP clock could be slowed down or the readback could be broken up into multiple smaller
transactions.
4. All DMA transactions must be 64-byte aligned to prevent accidently crossing a 4K byte boundary.
For more information regarding PL bitstream readback, see UG470
, 7 Series FPGAs Configuration
User Guide.
Loopback For Boot Image Transfers
The DMA controller is used to move boot images. Loopback is enabled by setting the devcfg.MCTRL
[INT_PCAP_LPBK] bit = 1; the boot image is read into the RxFIFO and written to another memory
location from the TxFIFO. The DMA source address can be to a linearly addressable flash device and
the destination can be OCM or DDR memory. The PL does not need to be powered-up to use the
loopback datapath. The datapath is illustrated in Figure 6-19.
Note: Caution should be taken in loopback mode when transferring boot images between slave
ports that prioritize writes over reads. This situation can lead to a DevC DMA hang condition.