User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 217
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
6.4.5 PL Control via User-JTAG
The user can initialize the PL by toggling the PROGRAM_B signal high-low-high. The PL asserts the
INIT_B pin while the PL is initializing after which time the INIT_B open drain pin is left to float high.
The user can then proceed with programming the PL by accessing the Xilinx TAP controller. The
control and status signals and the TAP controller connection is shown in Figure 6-20.
[PCFG_POR_CNT_4K] 29 RW
Power-up Reset Timer Rate Select. Timer is used during PL
initialization.
0: Use 64K timer. 1: Use 4K timer (faster initialization of reset
stage).
devcfg.MCTRL
[PCFG_POR_B] 8 RO PL power on/off indicator: 0: power is off. 1: power is on.
[INT_PCAP_LPBK] 4 RW PCAP Loopback: 0: disabled, 1: enabled.
devcfg.STATUS
[PCFG_INIT] 4 RO
PL initialization complete indicator:
0: not ready.
1: ready for bitstream programming.
Status interrupt for positive and negative edges:
[PCFG_INIT_{PE,NE}_INT].
Maskable using devcfg.INT_MASK [M_PCFG_INIT_{PE,NE}_INT].
devcfg.INT_STS
[PSS_CFG_RESET_B_INT] 27 WTC
PL reset interrupt detected, either edge.
Maskable using devcfg.INT_MASK [M_PSS_CFG_RESET_B_INT].
[PSS_CFG_RESET_B] 5 RO
PL Reset State indicator.
0: reset state. 1: not reset state.
[PCFG_POR_B_INT] 4 WTC
PL loss of power interrupt.
Maskable using devcfg.INT_MASK [M_PCFG_POR_B_INT].
[PCFG_CFG_RST_INT] 3 WTC
PL configuration module reset level interrupt.
Maskable using devcfg.INT_MASK [M_PCFG_CFG_RST_INT].
[PCFG_DONE_INT] 2 WTC
PL Programming Done Indicator.
0: PL is not available.
1: Bitstream programming is complete and PL is in user mode.
Maskable using devcfg.INT_MASK [M_PCFG_DONE_INT].
[PCFG_INIT_PE_INT] 1 WTC
INIT_B Signal Positive-edge Detector Interrupt.
Triggered when a positive edge is detected on the INIT_B signal.
Maskable using devcfg.INT_MASK [M_PCFG_INIT_PE_INT].
[PCFG_INIT_NE_INT] 0 WTC
INIT_B Signal Negative-edge Detector Interrupt.
Triggered when a negative edge is detected on the INIT_B signal.
Maskable using devcfg.INT_MASK [M_PCFG_INIT_NE_INT].
Table 6-23: PL Control and Status Register Bits (Cont’d)
Bit Field Bit Type Description