User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 219
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
6.5 Reference Section
This section includes content on these topics:
•Section 6.5.1 PL Configuration Considerations
•Section 6.5.2 Boot Time Reference
•Section 6.5.3 Register Overview
•Section 6.5.4 PS Version and Device Revision
6.5.1 PL Configuration Considerations
In master boot mode, the PL can be configured by PS software using the PCAP interface. Users are
free to configure the PL at any time, whether it is directly after PS boot using the FSBL/User code, or
at some later time using another image loaded into the PS memory. In JTAG boot mode, the PL can
be configured using the TAP controller. The PL configuration paths are illustrated in Figure 6-2,
page 157.
PCAP/ICAP/JTAG/User Access Exclusivity
The operation of the PCAP, ICAP and JTAG interfaces to the PL configuration module are mutually
exclusive. Care must be taken when switching among the three PL control paths: PCAP, JTAG and
ICAP, shown in Figure 6-2, page 157. Ensure that all outstanding transactions are completed before
changing interfaces.
Note: The user or external logic should not assert INIT_B when using the PS software to configure
the PL because the software does not have visibility to an external device delaying PL configuration.
Secure Mode PL Configuration
To perform a secure PL configuration, the PS must boot securely. The AES and HMAC units can only
be enabled by the BootROM. The procedure for loading a secure bitstream is the same as loading a
non-secure bitstream except the devcfg.CTRL [QUARTER_PCAP_RATE_EN] bit must be set = 1.
Because the AES unit only decrypts one byte at a time, the PCAP can only send one 32-bit word to
the PL for every four clock cycles.
Determine the PL State
The PL must first be powered on and initialized before it can be configured. When power is applied
to the PL, it begins its independent power-on reset sequence followed by initialization which clears
all of the PL configuration SRAM cells. The power-on reset status of the PL can be monitored by the
PS software.
The power status of the PL is tracked in the devcfg.MCTRL [PCFG_POR_B] bit. If the [PCFG_POR_B] bit
is set = 1, then the PL has power. The PL power status can also be tracked using the devcfg.INT_STS
[PCFG_POR_B_INT] interrupt.