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Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 220
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
Additional information about the PL power-up status can be obtained by reading the devcfg.STATUS
[PSS_CFG_RESET_B] register bit. If the bit is Low, then the PL is in a reset state. A transition from a Low
to a High indicates the start of the PL initialization process.
PL Initialization Time Optimization
The devcfg.CTRL [PCFG_POR_CNT_4K] control bit can be set by the FSBL/User code to improve the
initialization time of a PL power-up sequence that occurs after the FSBL/User code has had a chance
to execute. In this case, the FSBL/User code sets the [PCFG_POR_CNT_4K] control bit and initiates a
PL power-up sequence in secure or non-secure mode. This optimization is useful when the PL is
powered-up by the FSBL/User code for configuration. This control bit is not accessible through the
Register Initialization writes and is reset by all system resets (POR and non-POR).
This function is similar to asserting the OVERRIDE pin on a 7 series FPGA and may be referred to as
an override function. Additional information on the use of the [PCFG_POR_CNT_4K] bit is described
in UG821
, Zynq-7000 All Programmable SoC Software Developers Guide.
PCAP Clocking
The bitstream datapath to the PL configuration module is clocked by the PCAP clock, which is a
divided down PCAP_2x clock. The frequency range for the PCAP clock is specified in the data sheet.
To get a 100 MHz PCAP clock, program the PCAP_2x clock to 200 MHz.
PCAP Throughput
In non-secure mode, the transfer rate through the PCAP is approximately 145 MB/s. The PL
configuration module can accept data at the rate of 32 bits per PCAP clock, but the overall
throughput is limited by the PS AXI interconnect. This approximation assumes a 100 MHz PCAP
clock, a 133 MHz APB bus clock, a read issuing capability of 4 on the PS AXI interconnect, and a DMA
burst length of 8.
The throughput on the interconnect can be improved by about 20% by transferring the boot image
and bitstream from OCM memory and raising the CPU_1x clock rate by using a CPU clock ratio of
4:2:1. Refer to the data sheet for allowed clock rates.
In secure mode, the AES unit can only accept 8 bits per PCAP clock. To match this 8-bit data width
with the 32-bit datapath of the PCAP interface, software must set the devcfg.CTRL
[QUARTER_PCAP_RATE_EN] bit = 1. In this case, the demand for data by the PCAP interface is about
100 MB/s and is usually sustained by the PS AXI interconnect.
6.5.2 Boot Time Reference
Boot time activities include hardware activities, BootROM execution to configure the PS and load the
FSBL/User code, PL initialization and configuration, and the load and boot time of Linux or other
operating system. The factors that influence this boot process are summarized in Table 6-25. Boot
time is heavily influenced by:
• The bandwidth of the flash interface. This is based on the memory vendor specifications, board
parameters, and optimized register values.