User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 222
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
6.5.3 Register Overview
Table 6-26 provides an overview of the device configuration registers.
CRC check of
128 KB ROM
This is an eFuse option that causes the
BootROM to check the integrity of its own
code at the beginning of execution.
Requires about 26 ms to perform (PS_CLK
frequency = 33 MHz).
PL Hardware Functions
PL Voltage Ramp
This is power supply performance
specification. A typical board might have a
10 ms voltage ramp time.
The minimum ramp time is provided in the data
sheet.
PL Initialization
This can be done in parallel with the PS
power up, or be initiated by FSBL/User code.
If the FSBL/User code runs before PL initialization,
the time can be sped-up
(3)
.
PL T
POR
T
POR
occurs when the PL is powered-up. It
includes the PL Voltage Ramp time plus the
PL Initialization (cleaning/clearing) time.
This time is influenced by the performance of the
PL power supply and status of the PL. The range
for T
POR
is specified in the data sheet. If the PL is
already powered up then only the initialization
time is needed before programming the PL.
PL Configuration
This is done by FSBL/User code after the PL
has been initialized.
This time is influenced by many factors
(4)
.
PL Partial
Configuration
This is a special operation that programs
only part of the PL at a time. It is used for
very time-sensitive applications.
Contact your Xilinx FAE Sales Engineer to learn
more about partial configuration and
reconfiguration.
Notes:
1. The device type and model depend on the Boot Mode (e.g., for Quad-SPI, this includes ability to use linear addressing mode
for Flash devices ≤128Mb, or needing to use managed mode for larger devices).
2. The performance of the boot interface can be optimized by using the BootROM Header register initialization mechanism.
This is most effective in non-secure mode because more registers are accessible for optimization, see Table 6-7, page 174.
The register initialization can also be helpful in secure mode. The available optimizations are listed for each boot device in
section 6.3.3 BootROM Performance.
3. The PL initialization time can be decreased when the FSBL/User code executes before initializing the PL. Refer to “PL
Initialization Time Optimization” section in section 6.5.1 PL Configuration Considerations for information.
4. The PL configuration time is most dependent on whether the bitstream is encrypted or not. PL configuration time can be
reduced by using a compressed bitstream, but the size of the compressed file cannot be predicted nor can the time to
decompress the file be calculated.
5. For decryption or HMAC authentication, the PCAP configuration module must be operated at 1/4 the PCAP clock rate by
setting the devcfg.CTRL [QUARTER_PCAP_RATE_EN] bit = 1.
6. RSA authentication time depends from where the boot image and bitstream are sourced from and written to, the size of the
data, and the PS_CLK frequency. An example is shown in section 6.3.3 BootROM Performance, RSA Authentication Time.
Table 6-25: Factors that Affect Boot and Configuration Time (Cont’d)
Functional Area Description Boot Time Considerations
Table 6-26: DevC and Boot Registers
Function Description Hardware Register Type
Control and
configuration
Control devcfg.CTRL Read/Write
Sticky locks require POR to reset devcfg.LOCK R/Sticky Write
Configuration devcfg.CFG Read/Write