User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 225
UG585 (v1.11) September 27, 2016
Chapter 7: Interrupts
7.1.1 Private, Shared and Software Interrupts
Each CPU has a set of private peripheral interrupts (PPIs) with private access using banked registers.
The PPIs include the global timer, private watchdog timer, private timer, and FIQ/IRQ from the PL.
Software generated interrupts (SGIs) are routed to one or both CPUs. The SGIs are generated by
writing to the registers in the generic interrupt controller (GIC), refer to section 7.3 Register
Overview. The shared peripheral interrupts (SPIs) are generated by the various I/O and memory
controllers in the PS and PL. They are routed to either or both CPUs. The SPI interrupts from the PS
peripherals are also routed to the PL.
7.1.2 Generic Interrupt Controller (GIC)
The generic interrupt controller (GIC) is a centralized resource for managing interrupts sent to the
CPUs from the PS and PL. The controller enables, disables, masks, and prioritizes the interrupt
sources and sends them to the selected CPU (or CPUs) in a programmed manner as the CPU interface
accepts the next interrupt. In addition, the controller supports security extension for implementing a
security-aware system.
The controller is based on the ARM Generic Interrupt Controller Architecture version 1.0 (GIC v1),
non-vectored.
The registers are accessed via the CPU private bus for fast read/write response by avoiding
temporary blockage or other bottlenecks in the interconnect.
The interrupt distributor centralizes all interrupt sources before dispatching the one with the highest
priority to the individual CPUs. The GIC ensures that an interrupt targeted to several CPUs can only
be taken by one CPU at a time. All interrupt sources are identified by a unique interrupt ID number.
All interrupt sources have their own configurable priority and list of targeted CPUs.
7.1.3 Resets and Clocks
The interrupt controller is reset by the reset subsystem by writing to the PERI_RST bit of the
A9_CPU_RST_CTRL register in the SLCR. The same reset signal also resets the CPU private timers and
private watchdog timers (AWDT). Upon reset, all interrupts that are pending or being serviced are
ignored.
The interrupt controller operates with the CPU_3x2x clock (half the CPU frequency).
7.1.4 Block Diagram
The shared peripheral interrupts are generated from various subsystems that include the I/O
peripherals in the PS and logic in the PL. The interrupt sources are illustrated in Figure 7-2.