User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 229
UG585 (v1.11) September 27, 2016
Chapter 7: Interrupts
For an interrupt of level sensitivity type, the requesting source must provide a mechanism for the
interrupt handler to clear the interrupt after the interrupt has been acknowledged. This requirement
applies to any IRQF2P[n] (from PL) with a high level sensitivity type.
For an interrupt of rising edge sensitivity, the requesting source must provide a pulse wide enough
for the GIC to catch. This is normally at least 2 CPU_2x3x periods. This requirement applies to any
IRQF2P[n] (from PL) with a rising edge sensitivity type.
The ICDICFR2 through ICDICFR5 registers configure the interrupt types of all the SPIs. Each interrupt
has a 2-bit field, which specifies sensitivity type and handling model.
The SPI interrupts are listed in Table 7-4.
Table 7-4: PS and PL Shared Peripheral Interrupts (SPI)
Source Interrupt Name IRQ ID#
Status Bits
(mpcore Registers)
Required Type PS-PL Signal Name I/O
APU
CPU 1, 0 (L2, TLB, BTAC) 33:32 spi_status_0[1:0] Rising edge ~ ~
L2 Cache 34 spi_status_0[2] High level ~ ~
OCM 35 spi_status_0[3] High level ~ ~
Reserved ~ 36 spi_status_0[3] ~ ~ ~
PMU PMU [1,0] 38, 37 spi_status_0[6:5] High level ~ ~
XADC XADC 39 spi_status_0[7] High level ~ ~
DevC DevC 40 spi_status_0[8] High level ~ ~
SWDT SWDT 41 spi_status_0[9] Rising edge ~ ~
Timer TTC 0 44:42 spi_status_0[12:10] High level ~ ~
DMAC
DMAC Abort 45 spi_status_0[13] High level IRQP2F[28] Output
DMAC [3:0] 49:46 spi_status_0[17:14] High level IRQP2F[23:20] Output
Memory
SMC 50 spi_status_0[18] High level IRQP2F[19] Output
Quad SPI 51 spi_status_0[19] High level IRQP2F[18] Output
Reserved ~
~~
Always driven
Low
IRQP2F[17]
Output
IOP
GPIO 52 spi_status_0[20] High level IRQP2F[16] Output
USB 0 53 spi_status_0[21] High level IRQP2F[15] Output
Ethernet 0 54 spi_status_0[22] High level IRQP2F[14] Output
Ethernet 0 Wake-up 55 spi_status_0[23] Rising edge IRQP2F[13] Output
SDIO 0 56 spi_status_0[24] High level IRQP2F[12] Output
I2C 0 57 spi_status_0[25] High level IRQP2F[11] Output
SPI 0 58 spi_status_0[26] High level IRQP2F[10] Output
UART 0 59 spi_status_0[27] High level IRQP2F[9] Output
CAN 0 60 spi_status_0[28] High level IRQP2F[8] Output