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Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 230
UG585 (v1.11) September 27, 2016
Chapter 7: Interrupts
7.2.4 Interrupt Sensitivity, Targeting and Handling
There are three types of interrupts that come into the GIC as explained in section : SPI, PPI and SGI.
In a general sense, the interrupt signals includes a sensitivity setting, whether one or both CPUs
handle the interrupt, and which CPU or CPUs are targeted: zero, one, or both. However, the
functionality of most interrupt signals include fixed settings, while others are partially
programmable.
There are two sets of control registers for sensitivity, handling, and targeting:
• mpcore.ICDICFR[5:0] registers: sensitivity and handling. See Figure 7-4.
• mpcore.ICDIPTR[23:0] registers: targeting CPU(s). See Figure 7-5.
Shared Peripheral Interrupts (SPI)
The SPI interrupts can be targeted to any number of CPUs, but only one CPU handles the interrupt.
If an interrupt is targeted to both CPUs and they respond to the GIC at the same time, the MPcore
ensures that only one of the CPUs reads the active interrupt ID#. The other CPU receives the Spurious
ID# 1023 interrupt or the next pending interrupt, depending on the timing. This removes the
requirement for a lock in the interrupt service routine. Targeting the CPU is done by the ICDIPTR
[23:8] registers. The sensitivity of each SPI interrupt must be programmed to match those listed in
PL
PL [2:0] 63:61 spi_status_0[31:29]
Rising edge/
High level
IRQF2P[2:0]
Input
PL [7:3] 68:64 spi_status_1[4:0]
Rising edge/
High level
IRQF2P[7:3]
Input
Timer TTC 1 71:69 spi_status_1[7:5] High level ~ ~
DMAC DMAC[7:4] 75:72 spi_status_1[11:8] High level IRQP2F[27:24] Output
IOP
USB 1 76 spi_status_1[12] High level IRQP2F[7] Output
Ethernet 1 77 spi_status_1[13] High level IRQP2F[6] Output
Ethernet 1 Wake-up 78 spi_status_1[14] Rising edge IRQP2F[5] Output
SDIO 1 79 spi_status_1[15] High level IRQP2F[4] Output
I2C 1 80 spi_status_1[16] High level IRQP2F[3] Output
SPI 1 81 spi_status_1[17] High level IRQP2F[2] Output
UART 1 82 spi_status_1[18] High level IRQP2F[1] Output
CAN 1 83 spi_status_1[19] High level IRQP2F[0] Output
PL PL [15:8] 91:84 spi_status_1[27:20]
Rising edge/
High level
IRQF2P[15:8]
Input
SCU Parity 92 spi_status_1[28] Rising edge ~ ~
Reserved ~ 95:93 spi_status_1[31:29] ~ ~ ~
Table 7-4: PS and PL Shared Peripheral Interrupts (SPI) (Cont’d)
Source Interrupt Name IRQ ID#
Status Bits
(mpcore Registers)
Required Type PS-PL Signal Name I/O