User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 242
UG585 (v1.11) September 27, 2016
Chapter 8: Timers
The Status register shows whether the 24-bit counter reaches zero. Regardless of the WDEN bit in the
Zero Mode register, the 24-bit counter always keeps counting down to zero if it is not zero and the
selected clock source is present. Once it reaches zero, the WDZ bit of the Status register is set and
remains set until the 24-bit counter is restarted.
The prescaler block divides down the selected clock input. The CLKSEL signal is sampled at every
rising clock edge.
The internal 24-bit counter counts down to zero and stays at zero until it is restarted. While the
counter is at zero, the zero output signal is High.
Interrupt to PS Interrupt Controller
The pulse length from the SWDT (four CPU_1x clock cycles) is sufficient for the interrupt controller to
capture the interrupt using rising-edge sensitivity.
Reset
The watchdog reset is sent to the PS reset subsystem to cause a non-POR reset, see section
26.3 Reset Effects. The reset output to the MIO pin or EMIOWDTRSTO is active High.
TIP: To generate a signal pulse for the PS_POR_B and other board resets, route the EMIOWDTRSTO
signal from the SWDT through the PL and to a pin that can be externally latched to generate a valid
reset pulse. Alternatively, use an external watchdog timer device that is managed by PS software via a
GPIO output pin. The PS_POR_B reset pulse width requirements are defined in the data sheet.
8.4.4 Register Overview
A register overview of the SWDT is provided in Table 8-3.
Table 8-3: System Watchdog Timer Register Overview
Function Name Overview
Clock select slcr.WDT_CLK_SEL Selects between the CPU_1x and external clock source (MIO/EMIO).
MIO routing slcr.MIO_PIN_xx
Routes the SWDT clock input through the MIO multiplexer or EMIO if
no MIO routing.
Reset reason slcr.REBOOT_STATUS The [SWDT_RST] bit gets set when the SWDT generates a system reset.
Zero mode swdt.MODE
Enable SWDT, enable interrupt and reset outputs on timeout, set
output pulse lengths.
Reload values swdt.CONTROL Set the reload values for prescaler and 24-bit counter on timeout.
Restart swdt.RESTART Cause the prescaler and the 24-bit counter to reload and restart.
Status swdt.STATUS Indicates watchdog reaching zero.