User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 243
UG585 (v1.11) September 27, 2016
Chapter 8: Timers
8.4.5 Programming Model
System Watchdog Timer Enable Sequence
1. Select clock input source using the slcr.WDT_CLK_SEL[SEL] bit:
Ensure that the SWDT is disabled (swdt.MODE[WDEN] = 0) and the clock input source to be
selected is running before proceeding with this step. Changing the clock input source when the
SWDT is enabled results in unpredictable behavior. Changing the clock input source to a
non-running clock results in APB access hang.
2. Set the timeout period (Counter Control register):
The swdt.CONTROL[CKEY] field must be 0x248 to be able to write this register.
3. Enable the counter; enable output pulses; set up output pulse lengths (Zero Mode register):
The swdt.MODE[ZKEY] field must be 0xABC to be able to write this register. Ensure that IRQLN
meets the specified minimum values.
4. To run the SWDT with a different setting, disable the timer first (swdt.MODE[ZKEY] bit). Then
repeat steps 1, 2, and 3.
8.4.6 Clock Input Option for SWDT
The following code shows how the AP SoC selects the clock source for SWDT:
if slcr.WDT_CLK_SEL[0] is 0, use CPU_1X
else if slcr.MIO_PIN_14[7:0] is 01100000, use MIO pin 14
else if slcr.MIO_PIN_26[7:0] is 01100000, use MIO pin 26
else if slcr.MIO_PIN_38[7:0] is 01100000, use MIO pin 38
else if slcr.MIO_PIN_50[7:0] is 01100000, use MIO pin 50
else if slcr.MIO_PIN_52[7:0] is 01100000, use MIO pin 52
else use EMIOWDTCLKI
8.4.7 Reset Output Option for SWDT
The following code shows how the AP SoC selects the reset output pin for SWDT:
if slcr.WDT_CLK_sel[0] is 0, no output (to PS reset system only)
else if slcr.MIO_PIN_15[7:0] is 01100000, use MIO pin 15
else if slcr.MIO_PIN_27[7:0] is 01100000, use MIO pin 27
else if slcr.MIO_PIN_39[7:0] is 01100000, use MIO pin 39
else if slcr.MIO_PIN_51[7:0] is 01100000, use MIO pin 51
else if slcr.MIO_PIN_53[7:0] is 01100000, use MIO pin 53
else use EMIOWDTRSTO