User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 250
UG585 (v1.11) September 27, 2016
Chapter 9
DMA Controller
9.1 Introduction
The DMA controller (DMAC) uses a 64-bit AXI master interface operating at the CPU_2x clock rate to
perform DMA data transfers to/from system memories and PL peripherals. The transfers are
controlled by the DMA instruction execution engine. The DMA engine runs on a small instruction set
that provides a flexible method of specifying DMA transfers. This method provides greater flexibility
than the capabilities of DMA controller methods.
The program code for the DMA engine is written by software in to a region of system memory that
is accessed by the controller using its AXI master interface. The DMA engine instruction set includes
instructions for DMA transfers and management instructions to control the system.
The controller can be configured with up to eight DMA channels. Each channel corresponds to a
thread running on the DMA engine’s processor. When a DMA thread executes a load or store
instruction, the DMA Engine pushes the memory request to the relevant read or write queue. The
DMA controller uses these queues to buffer AXI read/write transactions. The controller contains a
multi-channel FIFO (MFIFO) to store data during the DMA transfers. The program code running on
the DMA engine processor views the MFIFO as containing a set of variable-depth parallel FIFOs for
DMA read and write transactions. The program code must manage the MFIFO so that the total depth
of all of the DMA FIFOs does not exceed the 1,024-byte MFIFO.
The DMAC is able to move large amounts of data without processor intervention. The source and
destination memory can be anywhere in the system (PS or PL). The memory map for the DMAC
includes DDR, OCM, linear addressed Quad-SPI read memory, SMC memory and PL peripherals or
memory attached to an M_GP_AXI interface.
The flow control method for transfers with PS memories use the AXI interconnect. Accesses with PL
peripherals can use the AXI flow control or the DMAC’s PL Peripheral Request Interface. There are no
peripheral request interfaces directed to the PS I/O Peripherals (IOPs). For the PL peripheral AXI
transactions, software running on a CPU is used in a programmed IO method using interrupts or
status polling.
The controller has two sets of control and status registers. One set is accessible in secure mode and
the other in non-secure mode. Software accesses these registers via the controller’s 32-bit APB slave
interface. The entire controller is either operated in secure or non-secure mode; there is no mixing of
modes on a channel basis. Security configuration changes are controlled by slcr registers and require
a controller reset to take effect.