User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 254
UG585 (v1.11) September 27, 2016
Chapter 9: DMA Controller
Instruction Cache
The controller stores instructions temporarily in a cache. When a thread requests an instruction from
an address, the cache performs a look-up. If a cache hit occurs then the cache immediately provides
the data, otherwise the thread is stalled while the controller uses the AXI interface to perform a
cache line fill from system memory. If an instruction is greater than four bytes, or spans the end of a
cache line, then it performs multiple cache accesses to fetch the instruction.
Note: When a cache line fill is in progress, the controller enables other threads to access the cache,
but if another cache miss occurs the pipeline is stalled until the first line fill is complete.
Note: Instruction cache latency for fill operations is dependent on the read latency of the system
memory where the DMA engine instructions are written. The performance of the DMAC is highly
dependent on the bandwidth of the 64-bit AXI master interface (CPU_2x clock).
Read/Write Instruction Queues
When a channel thread executes a load or store instruction the controller adds the instruction to the
relevant read queue or write queue. The controller uses these queues as an instruction storage buffer
prior to issuing transactions on the AXI interconnect.
Multi-channel Data FIFO
The DMAC uses a multi-channel first-in-first-out (MFIFO) data buffer to store data that it reads, or
writes, during a DMA transfer. Refer to 9.2.4 Multi-channel Data FIFO (MFIFO) for more information.
AXI Master Interface for Instruction Fetch and DMA Transfers
The program code is stored in a region of system memory that the controller accesses using the
64-bit AXI master interface. The AXI master interface also enables the DMA to transfer data from a
source AXI slave to a destination AXI slave.
APB Slave Interface for Register Accesses
The controller responds to two address ranges used by software to read and write the control and
status registers via the 32-bit APB slave interface.
• Non-secure register accesses
• Secure register accesses
Interrupt Interface
The interrupt interface enables efficient communications of events to the interrupt controller.
PL Peripheral DMA Request Interface
The PL peripheral request interface supports the connection of DMA-capable peripherals resident in
the PL. Each PL peripheral request interface is asynchronous to one another and asynchronous to the