User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 26
UG585 (v1.11) September 27, 2016
Chapter 1
Introduction
1.1 Overview
The Zynq®-7000 family is based on the Xilinx® All Programmable SoC (AP SoC) architecture. These
products integrate a feature-rich dual or single-core ARM® Cortex™-A9 MPCore™ based processing
system (PS) and Xilinx programmable logic (PL) in a single device, built on a state-of-the-art,
high-performance, low-power (HPL), 28 nm, and high-k metal gate (HKMG) process technology. The
ARM Cortex-A9 MPCore CPUs are the heart of the PS which also includes on-chip memory, external
memory interfaces, and a rich set of I/O peripherals.
The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance,
power, and ease of use typically associated with ASIC and ASSPs. The range of devices in the
Zynq-7000 AP SoC family enables designers to target cost-sensitive as well as high-performance
applications from a single platform using industry-standard tools. While each device in the
Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices. As a
result, the Zynq-7000 AP SoC devices are able to serve a wide range of applications including:
• Automotive driver assistance, driver information, and infotainment
• Broadcast camera
• Industrial motor control, industrial networking, and machine vision
• IP and smart camera
• LTE radio and baseband
• Medical diagnostics and imaging
• Multifunction printers
• Video and night vision equipment
The Zynq-7000 architecture conveniently maps the custom logic and software in the PL and PS
respectively. It enables the realization of unique and differentiated system functions. The integration
of the PS with the PL provides levels of performance that two-chip solutions (for example, an ASSP
with an FPGA) cannot match due to their limited I/O bandwidth, loose-coupling and power budgets.
Xilinx and the Xilinx Alliance partners offer a large number of soft IP modules for the Zynq-7000
family. Stand-alone and Linux device drivers are available for the peripherals in the PS and the PL
from Xilinx and additional OSes and board support packages (BSPs) from partners. The ISE® Design
Suite Embedded Edition development environment enables a rapid product development for
software, hardware, and systems engineers. Many third-party software development tools are also
available.