User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 261
UG585 (v1.11) September 27, 2016
Chapter 9: DMA Controller
9.2.4 Multi-channel Data FIFO (MFIFO)
The MFIFO is a shared resource utilized on a first-come, first-served basis by all currently active
channels. To a program, it appears as a set of variable-depth parallel FIFOs, one per channel, with the
restriction that the total depth of all the FIFOs cannot exceed the size of the MFIFO. The DMAC
maximum MFIFO depth is 128 (64-bit) words.
The controller is capable of realigning data from the source to the destination. For example, the
DMAC shifts the data by two byte lanes when it reads a word from address 0x103 and writes to
address 0x205. The storage and packing of the data in the MFIFO is determined by the destination
address and transfer characteristics.
When a program specifies that incrementing memory transfers are to be performed to the
destination, the DMAC packs data into the MFIFO to minimize the usage of the MFIFO entries. For
example, the DMAC packs two 32-bit words into a single entry in the MFIFO when the DMAC has a
64-bit AXI data bus and the program uses a source address of 0x100, and destination address of
0x200.
In certain situations, the number of entries required to store the data loaded from a source is not a
simple calculation of the amount of source data divided by MFIFO width. The calculation of the
number of entries required is not simple when any of the following occur:
• Source address is not aligned to the AXI bus width
• Destination address is not aligned to the AXI bus width
• Memory transfers are to a fixed destination, that is, a non-incrementing address
The DMALD and DMAST instructions each specify that an AXI bus transaction is to be performed. The
amount of data transferred by an AXI bus transaction depends on the values programmed in to the
CCRn register and the address of the transaction. Refer to the AMBA AXI Protocol Specification for
information about unaligned transfers.
Refer to section 9.3 Programming Guide for DMA Controller for considerations about MFIFO
utilization.
9.2.5 Memory-to-Memory Transfers
The controller includes an AXI master interface to access memories in the PS system, such as:
•OCM
• DDR
Through the same AXI central interconnect, the controller can potentially access the majority of the
peripheral subsystems. If a target peripheral can be seen as a memory-mapped region (or memory
port location) without a FIFO or need for flow control, then the DMAC can be used to read and write
to it. Typical examples include:
• QSPI in Linear addressing mode
•NOR flash
•NAND flash