User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 265
UG585 (v1.11) September 27, 2016
Chapter 9: DMA Controller
T7 The DMAC sets DMA{3:0}_DAVALID High and sets DMA{3:0}_DATYPE[1:0]
to indicate that the transaction is complete.
For more timing diagrams refer to ARM PrimeCell DMA Controller (PL330) Technical Reference
Manual: Peripheral Request Interface Timing Diagrams, keeping in mind that each PL peripheral
request interface is asynchronous to one another and asynchronous to the DMA itself.
9.2.8 PL Peripheral - Length Managed by PL Peripheral
The PL peripheral request interface enables a PL peripheral to control the quantity of data that an AXI
transfer contains, without the DMAC being aware of how many data cycles the transfer contains. The
PL peripheral controls the AXI transaction by using:
DMA{3:0}_DRTYPE[1:0] Selects a single or burst AXI Transaction
DMA{3:0}_DRLAST Notifies the DMAC when it commences the final request in the
current series
When the DMAC executes a DMAWFP instruction, it halts execution of the thread and waits for the PL
peripheral to send a request. When the PL peripheral sends the request, the DMAC sets the state of
the request flags depending on the state of the following signals:
DMA{3:0}_DRTYPE[1:0] The DMAC sets the state of the request_type flag:
00: request_type = Single
01: request_type = Burst
DMA{3:0}_DRLAST The DMAC sets the state of the request_last flag:
0: request_last = 0
1:request_last = 1
If the DMAC executes a DMAWFP single or DMAWFP burst instruction then the DMAC sets:
• The request_type{3:0} flag to Single or Burst, respectively
• The request_last{3:0} flag to 0
DMALPFE is an assembler directive which forces the associated DMALPEND instruction to have its nf
bit set to 0. This creates a program loop that does not use a loop counter to terminate the loop. The
DMAC exits the loop when the request_last flag is set to 1.
The DMAC conditionally executes the following instructions, depending on the state of the
request_type and request_last flags:
DMALD, DMAST, DMALPEND
When these instructions use the optional B|S suffix then the DMAC executes a DMANOP if
the request_type flag does not match.