User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 267
UG585 (v1.11) September 27, 2016
Chapter 9: DMA Controller
The DMAWFP burst instruction should be used when the program thread is required to halt
execution until the PL peripheral request interface receives a burst request. If the head entry request
type in the request FIFO is:
Single: The DMAC removes the entry from the FIFO and program execution remains halted.
Burst: The DMAC pops the entry from the FIFO and continues program execution.
The DMALDP instruction should be used when the DMAC is required to send an acknowledgement
to the PL peripheral when it completes the AXI read transaction. Similarly, the DMASTP instruction
should be used when the DMAC is required to send an acknowledgement to the PL peripheral when
it completes the AXI write transaction. The DMAC uses the DMA{3:0}_DATYPE[1:0] bus to
acknowledge the transaction to the PL peripheral {3:0}.
The DMAC sends an acknowledgement for a read transaction when rvalid and rlast are High and for
a write transaction when bvalid is High. If the system is able to buffer AXI write transactions, it might
be possible for the DMAC to send an acknowledgement to the PL peripheral, but the transaction of
write data to the end destination is still in progress.
The DMAFLUSHP instruction should be used to reset the request FIFO for the PL peripheral request
interface. After the DMAC executes DMAFLUSHP, it ignores PL peripheral requests until the PL
peripheral acknowledges the flush request. This enables the DMAC and PL peripheral to synchronize
with each other.
Refer to section 9.3 Programming Guide for DMA Controller for an example of microcode for DMA
length management.
9.2.10 Events and Interrupts
The DMAC supports 16 events. The first 8 of these events can be interrupt signals, IRQs [7:0]. Each of
the eight interrupts are outputs going to both the PS interrupt controller and the PL at the same
time. The events are used internal to the DMA engine to cross-trigger channel-to-channel or
manager-to-channel.
Table 9-2 shows the mapping between events and interrupts. Refer to the Interrupt Enable register in
Appendix B, Register Details for programming details.
When the DMA engine executes a DMASEV instruction it modifies the event/interrupt that the user
specifies.
• If the INTEN register sets the event/interrupt resource to function as an event, the DMAC
generates an event for the specified event/interrupt resource. When the DMAC executes a
DMAWFE instruction for the same event-interrupt resource then it clears the event.
Table 9-2: DMAC Events and Interrupts
DMAC
Event/IRQ #
System IRQ#
(to the PS)
IRQP2F
(to the PL)
DMA Engine
Event#
0 ~ 3 46 ~ 49 20 ~ 23 0 ~ 3
4 ~ 7 72 ~ 75 24 ~ 27 4 ~ 7
8 ~ 15 na na 8 ~ 15