User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 268
UG585 (v1.11) September 27, 2016
Chapter 9: DMA Controller
• If the INTEN register sets the event/interrupt resource to function as an interrupt, the DMAC
sets irq<event_num> High, where event_num is the number of the specified event-resource. To
clear the interrupt, the user must write to the INTCLR register. Refer to the Interrupt Clear
register in Appendix B, Register Details.
Refer to section 9.3 Programming Guide for DMA Controller for more information and Chapter 7,
Interrupts for more details about the System IRQs.
9.2.11 Aborts
An abort is sent to the CPUs via IRQ ID #45 and the PL peripheral via the IRQP2F[28] signal. Table 9-3
summarizes all of the possible causes for an abort. Table 9-3 explains the actions that the DMAC
takes after an abort condition. After an abort occurs the action the DMAC takes depends on the
thread type. Table 9-5 describes the actions that the processors or the PL peripheral must take after
the Abort signal is received. Refer to the ARM PrimeCell DMA Controller (PL330) Technical Reference
Manual: Aborts for details.
Table 9-3: DMAC Abort Types and Conditions
Abort Types Condition
Precise
The DMAC updates the PC
register with the address of the
instruction that created the
abort.
Note: When the DMAC signals a
precise abort, the instruction
that triggers the abort is not
executed; the DMAC executes a
DMANOP instead.
Security Violation on Channel Control Registers
A DMA channel thread in a non-secure state attempts to program the Channel Control
registers and generates a secure AXI bus transaction.
Security Violation on Events
A DMA channel thread in a non-secure state executes DMAWFE or DMASEV for an
event that is set as secure. The SLCR register TZ_DMA_IRQ_NS controls the security
state for an event.
Security Violation on PL Peripheral Request Interfaces
A DMA channel thread in a non-secure state executes DMAWFP, DMALDP, DMASTP, or
DMAFLUSHP for a PL peripheral request interface that is set as secure. The SLCR
register TZ_DMA_PERIPH_NS controls the security state for a PL peripheral request
interface.
Security Violation on DMAGO
The DMA manager in a non-secure state executes DMAGO to attempt to start a secure
DMA channel thread.
Error on AXI Master Interface
The DMAC receives an ERROR response on the AXI master interface when it performs
an instruction fetch. For example; trying to access reserved memory.
Error on Execution Engine
A thread executes an undefined instruction or executes an instruction with an operand
that is invalid for the configuration of the DMAC.