User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 269
UG585 (v1.11) September 27, 2016
Chapter 9: DMA Controller
Imprecise
The PC register might contain
the address of an instruction that
did not cause the abort occur.
Error on Data Load
The DMAC receives an ERROR response on the AXI master interface when it performs
a data load.
Error on Data Store
The DMAC receives an ERROR response on the AXI master interface when it performs
a data store.
Error on MFIFO
A DMA channel thread executes DMALD and the MFIFO is too small to store the data
or executes DMAST and the MFIFO contains insufficient data to complete the AXI
transaction.
Watchdog Abort
The DMAC can lock up if one or more DMA channel programs are running and the
MFIFO is too small to satisfy the storage requirements of the DMA programs.
The DMAC contains logic to prevent it from remaining in a state where it is unable to
complete a DMA transfer. The DMAC detects a lock up when all of the following
conditions occur:
• Load queue is empty
• Store queue is empty
• All of the running channels are prevented from executing a DMALD instruction
either because the MFIFO does not have sufficient free space or another channel
owns the load-lock
When the DMAC detects a lock up it signals an interrupt and can also abort the
contributing channels. The DMAC behavior depends on the state of the wd_irq_only
bit in the WD register. For more information,
refer to the subsection Resource
Sharing Between DMA Channels, page 286.
Table 9-3: DMAC Abort Types and Conditions (Cont’d)
Abort Types Condition
Table 9-4: DMAC Abort Handling
Thread Type DMAC Actions
Channel thread
Sets IRQ#45 interrupt and IRQP2F[28] signal High
Stops executing instructions for the DMA channel
Invalidates all cache entries for the DMA channel
Updates the Channel Program Counter registers to contain the address of the aborted
instruction provided that the abort was precise
Does not generate AXI accesses for any instructions remaining in the read queue and write
queue
Permits currently active AXI bus transactions to complete
DMA manager
Sets IRQ#45 interrupt and IRQP2F[28] signal High
Table 9-5: DMAC Thread Termination
Processor or PL Peripheral Actions
Reads the status of Fault Status DMA Manager register to determine if the DMA manager is faulting and to determine
the cause of the abort
Reads the status of Fault Status DMA Channel register to determine if a DMA channel is faulting and to determine the
cause of the abort