User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 274
UG585 (v1.11) September 27, 2016
Chapter 9: DMA Controller
Example: IRQ Interrupt Service Routine
The following steps need to be performed in this routine. This routine can support all 8 DMAC IRQs.
1. Check which event has caused the interrupt. Read dmac.INT_EVENT_RIS.
2. Clear the corresponding event. Write to the dmac.INTCLR register.
3. Inform the application that the DMA transfer has finished. Call the user callback function if
registered during DMA transfer setup.
Example: IRQ_ABORT Interrupt Service Routine
The following steps need to be performed in this routine.
1. Determine if a Manager fault occurred. Read dmac.FSRD. If the value of fs_mgr field is set, read
dmac.FTRD to know about the fault type.
2. Determine if a Channel fault occurred. Read dmac.FSRC. If the value of fault_status field for a
channel is set, read dmac.FTRx of the corresponding channel to know about the fault type.
3. Execute DMAKILL instruction. Do this for the DMA Manager or the DMA Channel Thread:
a. For the DMA Manager write the dmac.DBGINST0 register (refer to Appendix B, Register
Details) and enter the:
- Instruction byte 0 encoding for DMAKILL.
- debug_thread bit to 0. This selects the DMA manager.
b. For the DMA Channel Thread write the dmac.DBGINST0 register and enter the:
- Instruction byte 0 encoding for DMAKILL.
- channel_num bit set to the channel number to kill.
- debug_thread bit to 1. This selects the DMA channel thread.
c. Wait until the dbgstatus field in dmac.DBGSTATUS is busy.
d. Write 0x0 to the dmac.DBGCMD register to execute the instruction that the DBGINSTx
registers contain.
9.3.4 Register Overview
Table 9-10 provides an overview of the DMA Controller registers.
Table 9-10: DMAC Register Overview
Function Register Name Overview
DMAC Control dmac.XDMAPS_DS
dmac.XDMAPS_DPC
Provides the security state and the program counter.
Interrupts and Events dmac.INT_EVENT_RIS
dmac.INTCLR
dmac.INTEN
dmac.INTMIS
Enables/disables the interrupt detection, mask interrupt sent to
the interrupt controller, and reads raw interrupt status.