User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 276
UG585 (v1.11) September 27, 2016
Chapter 9: DMA Controller
9.4.1 Write Microcode to Program CCRx for AXI Transactions
The channel microcode is used to set the dmac.CCRx registers to define the attributes of the AXI
transactions. This is done using the DMAMOV CCR instruction.
The user should program the microcode to write to the dmac.CCR{7:0} register before it initiates a
DMA transfer. Here are the AXI attributes that the microcode writes:
1. Program the src_inc and dst_inc bit fields based on the type of burst (incrementing or fixed
address). This affects the ARBURST[0] and AWBURST[0] AXI signals.
2. Program the src_burst_size and dst_burst_size bit fields (number bytes per data beat on AXI).
This affects the ARSIZE[2:0] and AWSIZE[2:0] AXI signals.
3. Program the src_burst_len and dst_burst_len bit fields (number of data beats per AXI burst
transaction). This affects the ARLEN[3:0] and AWLEN[3:0] AXI signals.
4. Program the src_cache_ctrl and dst_cache_ctrl bit fields (caching strategy). This affects the
ARCACHE [2:0] and AWCACHE[2:0] AXI signals.
5. Program the src_prot_ctrl and dst_prot_ctrl bit fields (security state of the manager thread.) If the
manager thread is secure, ARPROT[1] should be set = 0 and if non-secure then it should be set
= 1. ARPROT[0] and ARPROT[2] values should be set = 0. For example:
-Set src_prot_ctrl = 0’b000 if DMA Manager is secure,
-Set scr_prot_ctrl = 0’b010 if DMA Manager is non-secure
6. Program endian_swap_size = 0 (no swapping).
9.4.2 Memory-to-Memory Transfers
This section shows examples of microcode that the DMAC executes to perform aligned, unaligned,
and fixed data transfers. Refer to Table 9-11 for aligned transfer, Table 9-12 for unaligned transfer,
and Table 9-13 for Fixed transfer. MFIFO utilization is also described.
Note: If cached memory is used for the DMA transfers, the programmer should ensure that the
cache coherency be maintained using appropriate cache operations. The cache entries
corresponding to the memory address range should be cleaned and invalidated before
programming DMA channel.