User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 279
UG585 (v1.11) September 27, 2016
Chapter 9: DMA Controller
Unaligned source address to aligned
destination address, with excess
initial load
This program is an alternative to that
described in unaligned source address
to aligned destination address. The
program uses a different sequence of
source bursts which might be less
efficient but requires fewer MFIFO
entries.
DMAMOV CCR, SB5 SS64
DB4 DS64
DMAMOV SAR, 0x1004
DMAMOV DAR, 0x4000
DMALD
DMAST
DMAMOV CCR, SB4 SS64
DB4 DS64
DMALP 14
DMALD
DMAST
DMALPEND
DMAMOV CCR, SB3 SS64
DB4 DS64
DMALD
DMAMOV CCR, SB1 SS32
DB4 DS64
DMALD
DMAST
DMAEND
The first DMALD instruction loads five
beats of data to enable the DMAC to
execute the first DMAST. After the first
DMALD, the subsequent DMALDs are
not aligned to the source burst size,
for example the second DMALD reads
from address 0x1028. After the loop,
the final two DMALDs read the data
required to satisfy the final DMAST.
This example has a static requirement
of one MFIFO entry and a dynamic
requirement of four MFIFO entries.
Aligned burst size, unaligned MFIFO
In this program the destination
address, which is narrower than the
MFIFO width, aligns with the burst size
but does not align with the MFIFO
width.
DMAMOV CCR, SB4 SS32
DB4 DS32
DMAMOV SAR, 0x1000
DMAMOV DAR, 0x4004
DMALP 16
DMALD
DMAST
DMALPEND
DMAEND
If the DMAC configuration has a 32-bit
AXI data bus width then this program
requires four MFIFO entries. However,
in this example the DMAC has a 64-bit
AXI data bus width and, because the
destination address is not 64-bit
aligned, it requires three rather than
the expected two MFIFO entries.
This example has a static requirement
of zero MFIFO entries and a dynamic
requirement of three MFIFO entries.
Table 9-12: DMAC Unaligned Transfers (Cont’d)
Description Code MFIFO Usage
Table 9-13: DMAC Fixed Transfers
Description Code MFIFO Usage
Fixed destination with aligned
address
In this program the source address
and destination address are aligned
with the AXI data bus width, and the
destination address is fixed.
DMAMOV CCR, SB2 SS64
DB4 DS32 DAF
DMAMOV SAR, 0x1000
DMAMOV DAR, 0x4000
DMALP 16
DMALD
DMAST
DMALPEND
DMAEND
Each DMALD in the program loads two
64-bit data transfers into the MFIFO.
Because the destination address is a
32-bit fixed address then the DMAC
splits each 64-bit data item across two
entries in the MFIFO.
This example has a static requirement
of zero MFIFO entries and a dynamic
requirement of four MFIFO entries.