User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 286
UG585 (v1.11) September 27, 2016
Chapter 9: DMA Controller
• SARn register so that it modifies the source byte lane alignment. For example, when the bus
width is 32 bits and bits [1:0] in the SARn register are changed.
When a discontinuity in the source datastream occurs, the DMAC:
1. Halts execution of the DMA channel thread.
2. Completes all outstanding read operations for the channel (just as if the DMAC was executing
DMARMB instruction).
3. Resumes execution of the DMA channel thread. No data is discarded from the MFIFO.
Resource Sharing Between DMA Channels
DMA channel programs share the MFIFO data storage resource. A set of concurrently running DMA
channel programs must not be started with a resource requirement that exceeds the configured size
of the MFIFO. If this limit is exceeded, the DMAC might lock up and generate a watchdog abort.
The DMAC includes a mechanism called the load-lock to ensure that the shared MFIFO resource is
used correctly. The load-lock is either owned by one channel, or it is free. The channel that owns the
load-lock can execute DMALD instructions successfully. A channel that does not own the load-lock
pauses at a DMALD instruction until it takes ownership of the load-lock.
A channel claims ownership of the load-lock when:
• It executes a DMALD or DMALDP instruction.
• No other channel currently owns the load-lock.
A channel releases ownership of the load-lock when any of the following controller actions occur:
• Executes a DMAST, DMASTP, or DMASTZ.
• Reaches a barrier, that is, it executes DMARMB or DMAWMB.
• Waits, that is, it executes DMAWFP or DMAWFE.
• Terminates normally, that is, it executes DMAEND.
• Aborts for any reason, including DMAKILL.
The MFIFO resource usage of a DMA channel program is measured in MFIFO entries, and rises and
falls as the program proceeds. The MFIFO resource requirement of a DMA channel program is
described using a static requirement and a dynamic requirement which are affected by the load-lock
mechanism.
ARM defines the static requirement to be the maximum number of MFIFO entries that a channel is
currently using before that channel does one of the following:
• Executes a WFP or WFE instruction.
• Claims ownership of the load-lock.
ARM defines the dynamic requirement to be the difference between the static requirement and the
maximum number of MFIFO entries that a channel program uses at any time during its execution.
To calculate the total MFIFO requirement, add the largest dynamic requirement to the sum of all the
static requirements.