User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 288
UG585 (v1.11) September 27, 2016
Chapter 9: DMA Controller
9.7 I/O Interface
9.7.1 AXI Master Interface
The AXI bus transaction attributes for caching, burst type and size, protection, etc are programmed
by microcode as described in section 9.4.1 Write Microcode to Program CCRx for AXI Transactions.
9.7.2 Peripheral Request Interface
The peripheral request interfaces support the connection of DMA-capable peripherals to enable
memory-to-peripheral and peripheral-to-memory DMA transfers to occur, without intervention from
a microprocessor. These peripherals must be in the PL and attached to the M_AXI_GP interface. All
peripheral request interface signals are synchronous to the respective clocks.
Table 9-16: DMAC Initialization Signals
Name Type Source Description
boot_manager_ns Input
SLCR register
TZ_DMA_NS
Controls the security state of the DMA manager, when the
DMAC exits from reset:
0: Assigns DMA manager to the secure state
1: Assigns DMA manager to the non-secure state
boot_irq_ns[15:0] Input
SLCR register
TZ_DMA_IRQ_NS
Controls the security state of an event-interrupt resource,
when the DMAC exits from reset:
• boot_irq_ns[x] is Low: Assigns event<x> or irq[x] to the
secure state
• boot_irq_ns[x] is High: Assigns event<x> or irq[x] to the
non-secure state
boot_periph_ns[3:0] Input
SLCR register
TZ_DMA_PERIPH_NS
Controls the security state of a peripheral request interface,
when the DMAC exits from reset:
• boot_periph_ns[x] is Low: Assigns peripheral request
interface x to the secure state
• boot_periph_ns[x] is High: Assigns peripheral request
interface x to the non-secure state
boot_addr[31:0] Input
Hard-wired
32'h0
Configures the address location that contains the first
instruction that the DMAC executes, when the DMAC exits
from reset.
Note: The DMAC only uses this address when boot_from_pc
is High.
boot_from_pc Input
Hard-wired
1'b0
Controls the location of where the DMAC executes its initial
instruction, after the DMAC exits from reset:
0: DMAC waits for an instruction from either APB interface
1: DMA manager executes the instruction that is located
at the address provided by boot_addr[31:0]